EKT 221/4 DIGITAL ELECTRONICS II Chapter 2 SEQUENCING AND CONTROL

Overview  Datapath and Control  Algorithmic State Machines (ASM)  ASM chart  Timing considerations  ASM chart examples - Binary multiplier  Hardwired Control  Control design methods  Sequence register and decoder  One flip-flop per state  Microprogrammed control

Introduction  Introduce the concept of the datapath for processing data and data implementation using register and register transfer  Digital system classified as programmable or non- programmable system depending on type of CU  Programmable – capable of executing programs  Non-programmable - have inputs, no mechanism for executing programs  Algorithmic State Machines (ASM) – state diagrams for a sequential circuit, provides representation of the behavior of CU as well as the controlled register transfers

Central Processing Unit  CPU contains three sections called the Arithmetic Logic Unit (ALU), the Control Unit (CU) and Registers.  CU: makes decisions and sends the appropriate signal down its lines to other parts of the computer. It controls the timing of operations in the computer and controls the instructions sent to the processor and the peripheral devices.  ALU: carries out arithmetic and logic functions. It carries out all the calculations and makes decisions on the data sent to the processor.  Registers: provide temporary memory storage locations within the processor.

Block Diagram of a Digital Computer MEMORY I/O CONTROL UNIT DATAPATH CPU

Introduction  CONTROL UNIT (CU) :  It controls communication and co-ordination between I/O devices. It reads and interprets instructions and determines the sequence for processing the data.  It directs the operation of the other units by providing timing and control signals.  It directs the flow of data between the CPU and other devices.  In modern computer designs, the CU is typically an internal part of the CPU with its overall role and operation unchanged.CPU  It implements the instruction set of the CPU. It performs the tasks of fetching, decoding, managing execution and, finally, storing results.instruction set  It may manage the translation of instructions (not data) to micro- instructions and manage scheduling the micro-instructions between the various execution units.

Types of Control Unit  2 types:  Programmable  Non-programmable  Programmable System  Input consist of sequence of instructions  Instruction are usually stored in memory (RAM or ROM)  Address comes from PC (Program Counter)  Non-programmable  Control unit is NOT responsible for getting instructions from memory or sequencing hence NO PC  CU determine the operation based on inputs and status bit from the datapath.

Datapath and Control Unit The control unit sends: – control signals – control outputs The control unit receives: – external control inputs – status signals Control Unit - Determines the enabling and sequencing of the operations Datapath - performs data transfer and processing operations as specified by a program

Algorithmic State Machine ASM)  A Flowchart is a convenient way to specify a sequence of procedural steps and decision paths for an algorithm.  ASM chart provides not only sequence of events, but it distinguished by the fact that it describes the timing relationship between states of the CU and the datapath actions in response to clock pulses.  By using register transfer in ASM, combined CU and datapath behavior is represented.

ASM Chart  4 basic elements:  State box  Scalar decision box  Conditional output box  Vector decision box

ASM Chart : State Box  Consist of a rectangle with:  The symbolic name for the state marked outside the upper left top  Containing register transfer operations and outputs activated within or while leaving the state  An optional state code, if assigned, outside the upper right top Entry Exit

ASM Chart : State Box Entry Exit Explanation:  The register transfer indicates that the register R is to be reset to 0 on any clock pulse that occurs while the control is in state IDLE.  RUN indicates that the ouput signal RUN is to be 1 during the time that the control in in state IDLE.

ASM Chart : Scalar Decision Box  Consist of a diamond with:  One input path (entry point).  One input condition, placed in the center of the box, that is tested. (in this case START)  A TRUE exit path taken if the condition is true (logic 1).  A FALSE exit path taken if the condition is false (logic 0). Entry Exit 0 Exit 1 (Refers to 1 bit condition)

ASM Chart: Conditional Output Box  Consist of an oval with:  One input path from a decision box or decision boxes.  One output path  Register transfers or outputs that occur only if the conditional path to the box is taken.

ASM Chart : Vector decision box  Consist of a hexagon with:  One Input Path (entry point).  A vector of input conditions, placed in the center of the box, that is tested.  Up to 2 n output paths. The path taken has a binary vector value that matches the vector input condition Entry Exit 0 Exit 1 Exit 2 Exit 2 n - 1

ASM Block  Consist of ONE State box and all of the decision and conditional output box connected between the state box exit and entry paths to the same or other boxes. Figure 8.2 : Morris Mano, pg 367

ASM Block ANALYSIS:  State IDLE, AVAIL = 1  START = 0, next state is IDLE  START = 1, next state, A is cleared to all 0’s  Depending on value of Q(1:0), next state is MUL0, MUL1, MUL2 or MUL3.  Note : The entry path and the five exit paths for the ASM block is labeled at the boundaries of the ASM block

ASM Block : Another Example ANALYSIS: State IDLE, AVAIL = 1 START = 0, next state is to Increase R and next state is IDLE START = 1, next to clear R to all 0’s and next state is… Depending on value of Q0, next state is MUL0 or MUL1.

ASM Timing Considerations  Refer to Figure 8.2  Using positive going transition (PGT), the timing diagram below is obtained. Fig. 8.3 : Morris Mano, pg 368

ASM Timing Considerations Analysis :  Clk cycle 1  Present state = IDLE  Output AVAIL = 1  Input START = 0  NEXT Clk cycle (beginning of clk cycle 2 PGT)  Content of Reg A unchanged, AVAIL = 1,  Clk cycle 2 (PGT)  Present state = IDLE  START = 1  NEXT Clk cycle (beginning of clk cycle 3 PGT)  Reg A = is cleared to 0  Q(1:0) is examined = 01  So path MUL1 is taken  Clk cycle 3 (PGT)  Present state = MUL1  Reg A = 0

ASM Timing - Conclusion  Outputs appear while in the state (in response to state and input values)  Register transfers occur at the clock while exiting the state – So, new value occur in the next state!

ASM : Binary Multiplier Example Partial Products are: 101 x x 0 Note: the partial product summation for n digits, base 2 numbers requires adding up to n digits (with carries) in a column. Note: n x m digit multiply generates up to an m + n digit result (same as decimal). Multiplicand Multiplier => x =

ASM : Binary Multiplier Example x 101 = MUL LSB with Multiplicand OR check if LSB = 1, if 1 then do addition 2.ADDITION (A + B) 3.SHIFT Right x 101 = x 101 = A Multiplier (Q)Multiplicand (B) A A 1.MUL LSB with Multiplicand OR check if LSB = 1, if 0 then do not do Addition 2.SHIFT Right Product 1.MUL LSB with Multiplicand OR check if LSB = 1, if 1 then do addition 2.ADDITION (A+B) 3.SHIFT Right Multiplicand (B) Multiplier (Q)

ASM : Binary Multiplier Example Multiplier (Q)Multiplicand (B) A Figure 8-6, Morris Mano, pg 371 Multiplicand is loaded into Reg. B Multiplier is loaded into Reg. Q Reg. A is initially zero Parallel Adder is used to add Reg. A and Reg B C FF’s stores Cout of P.A C is Reset to 0 upon shift right Counter P is provided to count the cycle If P=0 then read result in Reg. A and Reg. Q. and processing stops. CU stays in initial state until G=1 In the initial state, Reg. A and FF C is reset to 0. After Shifting Right, Reg. A will send the content to P.A for next cycle. The LSB of Q is discarded. CU will check for signal Z and Q0. CU will decide to add/shift or shift based on these 2 signals. The control signal from the CU to the datapath activate the required microoperations

Multiplier ASM Chart  Three main states are employed:  IDLE - state in which:  the outputs of the prior multiply is held until Q is loaded with the new multiplicand  input G is used as the condition for starting the multiplication, and  C, A, and P are initialized  MUL0 - state in which:  conditional addition is performed based on the value of Q0.  MUL1 - state in which:  right shift is performed to capture the partial product and position the next bit of the multiplier in Q0  the terminal count of 0 for down counter P is used to sense completion or continuation of the multiply.

Multiplier ASM Chart Figure 8.7 : Morris Mano, pg 373

Analysis of ASM Chart  ASM = IDLE and G=0, no action occurs  Multiplication ONLY occurs when G=1.  Moving to state MUL0, C & A are cleared to 0 and P is loaded with (n-1).  In state MUL0, a decision is made based on Q0:  Q0 = 1, B add to A, result transferred to A and Carry to C  Q0 = 0, A & C unchanged.  Note : Both condition will go to next state MUL1  A Shift Right is performed on the combined content of C, A and Q.

Analysis of ASM Chart  ASM = IDLE and G=0, no action occurs  Multiplication ONLY occurs when G=1.  Moving to state MUL0, C & A are cleared to 0 and P is loaded with (n-1).  In state MUL0, a decision is made based on Q0:  Q0 = 1, B add to A, result transferred to A and Carry to C  Q0 = 0, A & C unchanged.  Note : Both condition will go to next state MUL1  A Shift Right is performed on the combined content of C, A and Q.

Analysis of ASM Chart (cont.)  The shift transfer can be simplified to: C 0, C || A || Q sr C || A || Q  || is called concatenation, meaning it is a composite register or register made up of other registers.  Counter P is decremented in state MUL1. This illustrates a very IMPORTANT timing difference between a standard flowchart and an ASM chart.  The decision on Z, which represent P=0, follows the register transfer statement that updates P in the ASM chart.

Hardware selection  Identifying h/w is also important:  Reg. A = Shift Reg with parallel load, with CLR enable to reset the reg. to “0”.  Reg. Q = Shift Reg  C FF’s = accept input from Cout, with CLR enable to reset the FF to “0”.  Reg. B and Q = Parallel load Reg, used to load multiplier and multiplicand at the initial stage.

Alternate ASM Chart  Figure 8.8 (a) & (b), Morris Mano, pg 375.  Analyze the circuit.  It reduces the state to just 2. (IDLE and MUL1 only)  It utilizes the vector decision box.  (READ YOURSELF and Understand)

Hardwire Control  2 Aspect in implementing Control Unit (CU):  Control of microoperations(uO)  Sequencing CU with uO  Hence we divide ASM into 2 parts:  CONTROL TABLE : Table that defines Control signal in terms of states & inputs  SIMPLIFIED ASM : ASM Chart that only represents transitions from one state to another.

Control Table (Example for Binary Multiplier) Table 8.1 : Morris Mano, pg

Control Table (Example for Binary Multiplier) Table 8.1 : Morris Mano, pg 376 *Note : Parallel Adder & Zero Detect are microoperations Reg. B & Q need to be LOADED (IN) 1

2 *Note : Reg. B & Q need to be LOADED (IN) Analysis of ASM Chart with the Control Table. Write down all the operations corresponding to the hardware (FF, Registers and Counters)

3 Register A include 3 microoperations: Clear (A  0 ) Add & load (A  A + B) Right shift (sr) Since Clear operations always occurs at the same time as the clear of FF C and loading of counter P, all these uO can be activated by the same control : Initialize However, C is also cleared in state MUL1 so we separate the control signal : Clear_C

3 The Control Expression is determined by ASM chart. Since Initialize is 1 when G=1 and in state IDLE thus : IDLE. G Clear_C : G=1, state IDLE, state MUL_1 so the Control Expression is IDLE. G + MUL_1 Load and Shift_dec is define in similar manner Once written, do not need to duplicate, so control expression is dashed “ – ” Load_(reg) is loading the multiplier and multiplicand from outside input.

Simplified ASM Chart  Redraw the ASM Chart by removing the:  Microoperations  Conditional output  Condition box not affecting the next state Note : if the decision box is removed it goes to the same state

Simplified ASM Chart Figure 8.9 : Morris Mano, pg377

Designing of CU  Procedure specializations that use a single signal to represent each state.  2 methods: 1.Sequence Register and Decoder  Sequence register with encoded states  A reg. with n FF can have up to 2 n states  e.g.(n=2); state = 2 2 = 4 = 00, 01, 10, 11.  Decoder outputs produce “state” signals  An n-to-2 n decoder has up to 2 n outputs  e.g.(n=2); output = 2 to 4 = 0001,0010, 0100, One Flip-flop per State  A FF is assigned to each states  Flip-flop outputs as “state” signals, e. g., 0001, 0010,0100,  And at any one time only one FF can be 1.  The single 1 propagates from one FF to another under control of decision logic.

Sequencer and Decoder Design (Binary Multiplier Example)  2 inputs (G and Z) & 3 states (IDLE, MUL0 and MUL1)  2 FF’s and 2 to 4 line decoder (only 3 states so only 3 out of 4 decoder output will be used)  From this info, construct the sequencing table

Constructing the Sequencing Table  First, define:  States: IDLE, MUL0, MUL1  Input Signals : G, Z, Q0 (Q0 affects outputs, not next state)  Output Signals : Initialize, LOAD, Shift_Dec, Clear_C  State Transition Diagram (Refer to Simplified ASM Chart)  Output Function (Refer to Control Table)  Second, find  State Assignments (two bits required)  We will use two state bits to encode the three state IDLE, MUL0, and MUL1.

Assuming that state variables M1 and M0 are decoded into states, the next state part of the state table is: OR (refer to next slide) Constructing the Sequencing Table……cont. *NOTE : This method can be tedious if there are more FF’s in your design

We can derive directly from the ASM chart for input G and Z. Don’t care condition is designated as X Constructing the Sequencing Table……cont.

Extracting Equations From the table :- For M 0 next state = 1 D MO = IDLE.G + MUL1.Z For M1 next state = 1 D M1 = MUL0

Extracting Equations  The output equations using the decoded states:  Initialize = IDLE · G  Load = MUL0 · Q0  Clear_C = IDLE · G + MUL1  Shift_dec = MUL1

Building the CU D MO = IDLE.G + MUL1.Z D M1 = MUL0 Initialize = IDLE · G Load = MUL0 · Q0 Clear_C = IDLE · G + MUL1 Shift_dec = MUL1 Draw the decoder first with i/p from FF Draw FF M0 and M1 i/p and o/p connecting to decoder (don’t forget your clock) Draw o/p with coresponding i/p Draw your cct

Designing CU: One Flip-Flop per State Method  1 FF is assigned to each state  At any one time, only one FF is high, the rest contain 0 (low)  The design starts with the ASM chart, and replaces 1.State Boxes with flip-flops, 2.Scalar Decision Boxes with a DEMUX with 2 outputs, 3.Vector Decision Boxes with a (partial) DEMUX 4.Junctions with an OR gate, and 5.Conditional Outputs with AND gates.

1. State Box Transformation Rules  Each state box transforms to a D Flip- Flop  Entry point is connected to the input.  Exit point is connected to the Q output.

2. Scalar Decision Box Transformation Rules  Each Decision box transforms to a DEMUX  Entry points are "Enable" inputs.  The Condition is the "Select" input.  Decoded Outputs are the Exit points. DEMUX EN A0 D0 D1 Entry X Exit 0 Exit 1

3. Conditional Output Box Transformation Rules  Entry point is Enable input.  The Condition is the "Select" input.  Demultiplexer Outputs are the Exit points.  The Control OUTPUT is the same signal as the exit value.

4. Vector Decision Box Transformation Rules  Each Decision box transforms to a Demultiplexer  Entry point is Enable inputs.  The Conditions are the Select inputs.  Demultiplexer Outputs are the Exit points.

5. Junction Transformation Rules  Where two or more entry points join, connect the entry variables to an OR gate  The Exit is the output of the OR gate

Transformation 1.Replace each state with D FF (IDLE, MUL0 & MUL1) 2.Replace decision boxes with demultiplexer, decision variable as its selection input (G & Z), Q 0 use rule 3 as it’s condition goes to the same state 3.Each junction is replaced by an OR gate. 4.For output refer back to CU Table : Table 8.1 Initialize = IDLE · G Load = MUL0 · Q0 Clear_C = IDLE · G + MUL1 Shift_dec = MUL1

Transformation 1.State Box  D FF 2.Decision Box  Demux 3.Junction  OR gate 4.Conditional  AND gate Corrections: Demux Z, D0 goes to MUL0 D1 goes to MUL1 Initialize = IDLE · G Load = MUL0 · Q0 Clear_C = IDLE · G + MUL1 Shift_dec = MUL1

Speeding up the Multiplier  In processing each bit of the multiplier, the circuit visits states MUL0 and MUL1 in sequence.  By redesigning the multiplier, is it possible to visit only a single state per bit processed?  Remember the Alternative ASM (try and do it yourself at home)

Alternative ASM (2 States)

Microprogrammed Control  Microprogrammed Control — a control unit with binary control values stored as words in memory.  Microinstructions — words in the control memory.  Microprogram — a sequence of microinstructions.  Control Memory — RAM or ROM memory holding the microinstructions.  Writeable Control Memory — RAM Memory into which microinstructions may be written

Microprogrammed CU Organization Fig. 8.17: Morris Mano, pg 391 Control Memory is assumed to be a ROM which all control microprograms are permanently stored. The control address register (CAR) specifies the add. of the microinstructions. The control data register (CDR), which is optional, may hold the microinstructions currently being executed by the datapath and the CU When a microinstruction is executed, the next-address generator (NAG) produces the next address. The NAG + CAR is sometimes called a microprogram sequencer.

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