1. ENG241 Digital Design Week #10 Sequencing and Control

2. Fall 2014ENG241/Digital Design2 Week #10 Topics  The Control Unit  Algorithmic State Machines  ASM Elements  Hardwired Control I. One Flip-Flop Per State II. Sequence Register and Decoder  VHDL Representation

3. Fall 2014ENG241/Digital Design3 Resources  Chapter #8, Mano Sections 8.1 The Control Unit 8.2 Algorithmic State Machines 8.3 ASM Examples 8.4 Hardwired Control

4. Fall 2014ENG241/Digital Design4 Parts of CPUs  Datapath  The registers and logic to perform operations on them  Control unit  Generates signals to control datapath ControlData Path

5. Fall 2014ENG241/Digital Design5 The Control Unit  The binary information stored in a digital computer can be classified as either data or control information. 1. Data is manipulated in a data-path  To perform arithmetic, logic, shifting, and other data-processing tasks.  These operations are implemented with ALUs, registers, multiplexers, and busses. 2. The control unit  Provides signals that activate the various micro- operations in the data-path to perform the specified data processing tasks.  The control unit also determines the sequence in which the various actions are performed (i.e. when they are to be performed)

6. Fall 2014ENG241/Digital Design6 Control Unit Types  Two distinct classes: Programmable Non-programmable.  A programmable control unit has: An external ROM or RAM array for storing instructions and control information A program counter (PC) or other sequencing register with contents that points to the next instruction to be executed Decision logic for determining the sequence of operations and logic to interpret the instructions  A non-programmable control unit (hardwired Control) does not fetch instructions from a memory but  just determines the operations to be performed and the sequence of those operations based only on inputs and status bits. non-programmable  In ENGG2410 we are mainly concerned with the design of a non-programmable control unit.

7. Fall 2014ENG241/Digital Design7 Algorithmic State Machines  The function of a state machine (or sequential circuit) can be represented by a state table or a state diagram.  What is wrong with state diagrams?  Solution?  A flowchart is a way of showing actions and control flow in an algorithm.  An Algorithmic State Machine (ASM) is simply a flowchart-like way to specify state diagrams for sequential logic and, optionally, actions performed in a datapath.  While flowcharts typically do not specify “time”, an ASM explicitly specifies a sequence of actions and their timing relationships.

8. Fall 2014ENG241/Digital Design8 ASM Primitives 1. State Box (a rectangle) 2. Scalar Decision Box (a diamond) 3. Vector Decision Box (a hexagon) 4. Conditional Output Box (oval).  The State Box is a rectangle, marked with the symbolic state name, containing register transfers and output signals activated when the control unit is in the state.  The Scalar Decision Box is a diamond that describes the effects of a specific input condition on the control. It has one input path and two exit paths, one for TRUE (1) and one for FALSE (0).  The Vector Decision Box is a hexagon that describes the effects of a specific n-bit (n > 2) vector of input conditions on the control. It has one input path and up to 2 n exit paths, each corresponding to a binary vector value.  The Conditional Output Box is an oval with entry from a decision block and outputs activated for the decision conditions being satisfied.

9. Fall 2014ENG241/Digital Design9  A rectangle with:  The symbolic name for the state marked outside the upper left top  Containing register transfer operations and outputs activated within or while leaving the state  An optional state code, if assigned, outside the upper right top (Symbolic Name) IDLE (Register transfers or outputs) R ← 0 RUN (Optional state co de) 0000 State Box

10. Fall 2014ENG241/Digital Design10  A diamond with:  One input path (entry point).  One input condition, placed in the center of the box, that is tested.  A TRUE exit path taken if the condition is true (logic 1).  A FALSE exit path taken if the condition is false (logic 0). (Input) START (True Condition) (False Condition) 0 1 Scalar Decision Box

11. Fall 2014ENG241/Digital Design11 Vector Decision Box  A hexagon with:  One Input Path (entry point).  A vector of input conditions, placed in the center of the box, that is tested.  Up to 2 n output paths. The path taken has a binary vector value that matches the vector input condition (Vector of Input Conditions) (Binary Vector Values) 00 01 (Binary Vector Values) 10 Z, Q0

12. Fall 2014ENG241/Digital Design12 Conditional Output Box  An oval with:  One input path from a decision box or decision boxes.  One output path  Register transfers or outputs that occur only if the conditional path to the box is taken.  Transfers and outputs in a state box are Moore type - dependent only on state  Transfers and outputs in a conditional output box are Mealy type - dependent on both state and inputs (Register transfers or outputs) R ← 0 RUN From Decision Box(es)

13. Fall 2014ENG241/Digital Design13  By connecting boxes together, we begin to see the power of expression.  What are the: I. States? II. Inputs? III. Outputs? IV. Conditional Outputs? V. Transfers? VI. Conditional Transfers? Connecting Boxes Together IDLE R← 0 START 01 PC ← 0 A VAIL INIT

14. Fall 2014ENG241/Digital Design14 ASM Blocks  One state box along with all decision and conditional output boxes connected to it is called an ASM Block.  The ASM Block includes all items on the path from the current state to the same or other states. IDLE AVAIL START R← R + 1 R ← 0 Q0 0 1 MUL0 MUL1 ASM BLOCK Entry Exit

15. Fall 2014ENG241/Digital Design15 From State Diagram to ASM ABC S = 0 S = 1 Z = 0 Z = 1

16. Fall 2014ENG241/Digital Design16 From State Diagram to ASM A00 S 01 B C 01 10 Z 01 ABC S = 0 S = 1 Z = 0 Z = 1

17. Fall 2014ENG241/Digital Design17  Find the ASM chart corresponding to the following description 1. There are two states A, B 2. If in state A and input X is `0’ then the next state is A 3. If in state A and input X is `1’ then the next state is B 4. If in state B and input Y is `1’ then the next state is B 5. If in state B and input Y is `0’ then the next state is A 6. Output Z is equal to `1’ while the circuit is in state B  Solution: 1. Total States  2 2. Two Inputs  X, Y 3. One Output  Z Example (1)

18. Fall 2014ENG241/Digital Design18 ASM for Example (1) 0 A B X Z = 1 Y 1 1 0

19. Fall 2014ENG241/Digital Design19  Designing the Control Unit: I. One Flip-flop per State A flip-flop is assigned to each of the states and at any time, only one of the flip flops contains a 1, with all the rest containing 0. II. Sequence Register and Decoder Uses a sequence register for the control states and a decoder to provide an output signal corresponding to each of the states. Hardwired Control

20. Fall 2014ENG241/Digital Design20  As the name implies the method uses one flip-flop per state and a simple set of transformation rules to implement the circuit.  The design starts with the ASM chart,  Then all you do is replace: 1. A State Box with a D flip-flop, 2. A Scalar Decision Box with a demultiplexer with 2 outputs, 3. A Vector Decision Box with a (partial) demultiplexer 4. Any Junction with an OR gate, and 5. Any Conditional Output with an AND gate (for a Mealy Machine!!) I. One Flip-Flop per State

21. Fall 2014ENG241/Digital Design21 State Box Transformation Rules  Each state box transforms to a D Flip-Flop  Entry point is connected to D FF input.  Exit point is connected to the D FF `Q’ output.

22. Fall 2014ENG241/Digital Design22 Scalar Decision Box Transformation Rules  Each Decision box transforms to a Demultiplexer  Entry points are "Enable" inputs.  The Condition is the "Select" input.  Decoded Outputs are the Exit points.

23. Fall 2014ENG241/Digital Design23 Vector Decision Box Transformation Rules  Each vector decision box transforms to a Demultiplexer  Entry point is Enable inputs.  The Conditions are the Select inputs.  Demultiplexer Outputs are the Exit points. (Vector of Input Conditions) (Binary Vector Values) 00 01 (Binary Vector Values) 10 X 1, X 0 X1X1 Entry Exit 0 Exit 1 X0X0 DEMUX EN A1A1 A0A0 D0D0 D2D2 D1D1 D3D3 Exit2 Exit 3

24. Fall 2014ENG241/Digital Design24 Junction Transformation Rules  Where two or more entry points join, connect the entry variables to an OR gate  The Exit is the output of the OR gate

25. Fall 2014ENG241/Digital Design25 Conditional Output Box Rules  Entry point is Enable input.  The Condition is the "Select" input.  Demultiplexer Outputs are the Exit points.  The Control OUTPUT is the same signal as the exit value.

26. Fall 2014ENG241/Digital Design26 A00 S 01 B C 01 10 Z 01 Implement using 1 Flip Flop Per State  Note: One FF is assigned to each of the states, and at any time, only one of the FFs contains a 1, with all the rest containing 0.  When a 1 is in the FF assigned to a particular state, the sequential circuit is in that same state.  The single 1 propagates from one FF to another under the control of decision logic

27. Fall 2014ENG241/Digital Design27 One Flip Flop Per State D C OR DeMux D D C C S OR DeMux Z A 00 S 0 1 B C 01 10 Z 0 1

28. Fall 2014ENG241/Digital Design28  This method uses a decoder and a set of flip flops (or a register) to implement the circuit. I. The design starts with the ASM chart, II. According to the number of states 2 n, we will use n flip flops (log 2 # state) III. Construct State Table (directly from ASM) IV. Use an n-to-2 n decoder  has 2 n outputs Sequence Register and Decoder

29. Fall 2014ENG241/Digital Design29 A00 S 01 B C 01 10 Z 01 Implement  Sequence Register/Decoder How many Flip Flops? Decoder Size?

30. Fall 2014ENG241/Digital Design30 Implement  Sequence Register/Decoder D D C C M0M0 M1M1 0 1 2 3 Decoder A B C X Sequence Register

31. Fall 2014ENG241/Digital Design31 State Table: Construction Present State NameM1M1 M0M0 A00 00 B01 C10 10 X11 Inputs SZ 0x 1x xx x0 x1 xx Next State M1M1 M0M0 00 01 10 10 00 xx Decoder Outputs ABC 100 100 010 001 001 xxx

32. Fall 2014ENG241/Digital Design32 Sequence Register and Decoder Present StateInputsNext StateDecoder Outputs NameM1M1 M0M0 SZM1M1 M0M0 ABC A000x00100 001x01100 B01xx10010 C10x010001 10x100001 X11xxxxxxx

33. Fall 2014ENG241/Digital Design33 Implement  Sequence Register/Decoder D M0 = A.S D M1 = B + C.Z’

34. 34 Implement  Sequence Register/Decoder D D C C A0A0 A1A1 0 1 2 3 Decoder S D M1 = B + C.Z’ Z’ A B C D M0 = A.S

35. Fall 2014ENG241/Digital Design35  At first glance, it may seem that the one FF per state method would increase the cost of the system, since more flip-flops are used.  But the method offers some cost advantages that may not be apparent:  One advantage is the simplicity with which the logic can be designed – merely by inspection of the ASM chart or state diagram.  No state or excitation tables are needed if D flip-flops are employed.  This offers a savings in design effort, an increase in logic simplicity. One FF per State vs. Sequence Register and Decoder

36. Fall 2014ENG241/Digital Design36 VHDL Code Process that will depend on clock event to reset system to Idle State and implement state_register based on CLK Process that will act as a sequencer that will dictate the state you are in given the input Process that will control your data path (If you have a data path!) Similar to Sequencer P1 P3 P2

37. Fall 2014ENG241/Digital Design37 Implement  Using VHDL X Y Z IDLE00 G 01 LOAD 01 10 S 01 ADD What are the Inputs? Remember that this is a state machine and we have to start somewhere at power up!

38. Fall 2014ENG241/Digital Design38 VHDL Code -- VHDL Code entity declaration library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity sequential_machine is port (CLK, RESET, G, S : in std_logic; X,Y, Z : out std_logic); end sequential_machine;

39. Fall 2014ENG241/Digital Design39 VHDL Code: Architecture -- VHDL Code Architecture architecture behavior of sequential_machine is type state_type is (IDLE, LOAD, ADD); signal state, next_state : state_type; begin end behavior ; State_register: process (CLK)..... Next_state_func: process (G,S,state)...... Datapath_func: process (CLK)......

40. Fall 2014ENG241/Digital Design40 VHDL Code: State-Register Process -- VHDL Code State Register Process State_Register: process (CLK, RESET) begin if (RESET = ‘1’) then state <= IDLE; elsif (CLK'event and (CLK = '1')) then state <= next_state; end if ; end process;

41. Fall 2014ENG241/Digital Design41 VHDL Code: Next-State Process -- VHDL Code for next_state_func next_state_func: process (G,S,state) begin case state is when IDLE => if G = ‘1’ then next_state <= LOAD; else next_state <= IDLE; end if; when LOAD => next_state <= ADD; when ADD => if S = ‘1’ then next_state <= IDLE; else next_state <= ADD; end if; end case end process; X Y Z IDLE00 G 01 LOAD 01 10 S 01 ADD

42. Fall 2014ENG241/Digital Design42 VHDL Code: datapath Process -- VHDL Code for datapath_func Output_func: process (state) begin case state is when IDLE => X <= 1; when LOAD => Y <= 1; when ADD => Z < =1 end case end process; X Y Z IDLE00 G 01 LOAD 01 10 S 01 ADD

43. Fall 201443 Multiplier Example: ASM Chart 01 G IDLE MUL0 01 Z MUL1 01 0C ←0, A ← P ← n –1 A ←A +B, C ←C out P ←P – 1 C ← 0, C || A || Q ← sr C || A || Q, Q 0 Complicated!!

44. Fall 2014ENG241/Digital Design44 Multiplier Example: Control Unit  In implementing a complex control unit, designers usually have to deal with (separate) two distinct aspects control signals  The generation of the control signals  Sequencing  Sequencing of the operations (what will happen next)  We can separate the two aspects by dividing the original ASM specification into two parts: table that defines the control signals  A table that defines the control signals in terms of states and inputs simplified ASM chart  A simplified ASM chart that represents only transitions from state to state

45. Fall 201445 Multiplier Example: ASM Chart 01 G IDLE MUL0 01 Z MUL1 01 0C ←0, A ← P ← n –1 A ←A +B, C ←C out P ←P – 1 C ← 0, C || A || Q ← sr C || A || Q, Q 0

46. Fall 201446 Example - Sequencing Part of ASM 0 1 IDLE MUL0 0 1 01 MUL1 10 00 G Z

47. 47 Multiplier Example: Flip-flop per State Design Logic Diagram 01 IDLE MUL0 01 01 MUL1 10 00 G Z

48. Fall 2014ENG241/Digital Design48 Sequencer and Decoder Design IDLE MUL0 MUL1 Initialize Clear_C Shift_dec M 0 Load M 1 G Z Q 0 DECODER A0 A1 0 3 2 1 D C D C START

49. Fall 2014ENG241/Digital Design49 mMicrooperations from Ta Binary Coo Summary  Control units are an essential part of any CPU.  Control units can either be programmable or non-programmable.  Non-programmable CU:  One FF per state  Sequence Register and Decoder.  Obtaining the ASM is the key to designing any control unit.  Use the process statement to implement any sequential circuit, state diagrams and algorithmic state machines.

50. Fall 2014ENG241/Digital Design50

51. Fall 2014ENG241/Digital Design51  Find an ASM chart for a traffic light controller that works as follows: I. A timing signal T is the input to the controller II. T defines the yellow light as well as the changes of RED and GREEN lights III. While T = 0, the green light is on for one signal, the red light is on for other signal IV. While T = 1, the yellow light is on for the signal that was previously green and the signal that was previously red remains red V. When T becomes 0, the signal that was previously yellow becomes RED and the signal that was previously RED becomes GREEN VI. This pattern continues Example (Traffic Light Controller)

52. Fall 2014ENG241/Digital Design52  While T = 0, the green light is on for one signal, the red light is on for other signal  While T = 1, the yellow light is on for the signal that was previously green and the signal that was previously red remains red  When T becomes 0, the signal that was previously yellow becomes RED and the signal that was previously RED becomes GREEN  This pattern continues Example (Traffic Light Controller)

53. Fall 2014ENG241/Digital Design53 ASM for Traffic Light Controller 01 GREEN RED YELLOW RED GREEN RED YELLOW TTTT 000111 Implement using One Flip Flop Per State Implement using Sequence Register and Decoder

54. Fall 2014ENG241/Digital Design54 mMicrooperations from Ta Binary Coo II Micro-Programmed Control  A control unit with its binary control values stored as words in memory is called a micro- programmed control.  Each word in the control memory contains a microinstruction that specifies one or more micro-operations for the system.  A sequence of microinstructions constitutes a micro-program.  A micro-program is often fixed at the time of the system design and so is usually stored in ROM.  A micro-program can also be written in RAM but has to be loaded initially at system startup.

55. Fall 2014ENG241/Digital Design55 mMicrooperations from Ta Binary Coo A Micro-Programmed Control Unit Organization 1. Control Address Register (CAR) specifies the address of the microinstruction. 2. The control data register (CDR) may hold the instruction currently being executed. 3. The next address generator produces the next address.

56. Fall 2014ENG241/Digital Design56 Multiplier Example  Example: (101 x 011) Base 2  Note that the partial product summation for n digits, base 2 numbers requires adding up to n digits (with carries) in a column.  Note also n x m digit multiply generates up to an m + n digit result (same as decimal). Partial products are: 101 x 0, 101 x 1, and 101 x 1

57. Fall 2014ENG241/Digital Design57 Example (1 0 1) x (0 1 1) Again  Reorganizing example to follow hardware algorithm: 101 x 011 0000 + 101 0101 00101 + 101 01111 001111 0001111 Clear C || A Multipler 0 = 1 => Add B Addition Shift Right (Zero-fill C) Multipler 1 = 1 => Add B Addition Shift Right Multipler 2 = 0 => No Add, Shift Right

58. Fall 2014ENG241/Digital Design58 Hardware ? (Data Path + Control) 1. A Parallel Adder 2. Switches to enter Multiplier/Multiplicand 3. Shift Register Q (Multiplier) 4. Register B (Multiplicand) 5. Counter (to know when to stop) 6. Zero detection circuit (input to control) 7. Shift Register A (scratch pad) 8. Flip Flop to store Carry of Adder 9. Detect when Q 0 is zero or one (input to control) 10. A Go signal to start (input to control) 11. Control Output?  Load, Load_B, Clear_C, Initialize_A, Shift

59. Fall 2014ENG241/Digital Design59 Multiplier Example: Block Diagram C out n n n 2 1 Counter P Zero detect Control unit G (Go) log 2 n Q o Z Parallel adder Multiplicand Register B Shift register A 0 CShift register Q Multiplier Product OUT IN Control signals n nn 4

60. Fall 2014ENG241/Digital Design60 Multiplexer Example: Operation 1. The multiplicand (top operand) is loaded into register B (X) 2. The multiplier (bottom operand) is loaded into register Q (X) 3. Register C|| A is initialized to 0 when G becomes 1. 4. The partial products are formed in register C||A||Q. 5. Each multiplier bit, beginning with the LSB, is processed (if bit is 1, use adder to add B to partial product; if bit is 0, do nothing) 6. C||A||Q is shifted right using the shift register Partial product bits fill vacant locations in Q as multiplier is shifted out If overflow during addition, the outgoing carry is recovered from C during the right shift 7. Steps 5 and 6 are repeated until Counter P = 0 as detected by Zero detect. Counter P is initialized in step 4 to n – 1, n = number of bits in multiplier

61. Fall 2014ENG241/Digital Design61 Multiplier Example: ASM Chart (continued)  Three states are employed using a Mealy output model:  IDLE - state in which:  input G is used as the condition for starting the multiplication, and  C, A, and P are initialized  MUL0 - state in which conditional addition is performed based on the value of Q 0.  MUL1 - state in which:  right shift is performed to capture the partial product and position the next bit of the multiplier in Q 0  the terminal count of 0 for down counter P is used to sense completion or continuation of the multiply.

62. Fall 2014ENG241/Digital Design62 Multiplier Example: ASM Chart 01 G IDLE MUL0 01 Z MUL1 01 0C ←0, A ← P ←P ← n –1 A ←A +B, C ←C out P ←P ←P – 1 C ← 0, C || A || Q ← sr C || A || Q, Q 0

63. Fall 2014ENG241/Digital Design63 Multiplier Example: Control Unit  In implementing a complex control unit, designers usually have to deal (separate) two distinct aspects  The generation of the control signals  Sequencing of the operations (what will happen next)  We can separate the two aspects by dividing the original ASM specification into two parts:  A table that defines the control signals in terms of states and inputs  A simplified ASM chart that represents only transitions from state to state

64. Fall 2014ENG241/Digital Design64 Multiplier Example: Control Signal Table Block Diagram Module RegisterA: B: Flip-FlopC RegisterQ CounterP:

65. Fall 2014ENG241/Digital Design65 Multiplier Example: Control Signal Table Block Diagram ModuleMicrooperation RegisterA:A ← 0 A ← A + B C ||A Q srC ||A Q RegisterB:B ←IN Flip-FlopC: C ← 0 C ←C out RegisterQ: Q ←IN C ||A Q ← srC ||A Q CounterP:P ←n – 1 P ← P – 1 ←

66. Fall 2014ENG241/Digital Design66 Multiplier Example: Control Signal Table Block Diagram ModuleMicrooperation Control Signal Name RegisterA:A ← 0Initialize A ← A + B C ||A Q srC ||A QShift_dec RegisterB:B ←INLoad_B Flip-FlopC: C ← 0Clear_C C ←C out Load RegisterQ: Q ←INLoad_Q C ||A Q ← srC ||A QShift_dec CounterP:P ←n – 1Initialize P ← P – 1Shift_dec ← Load

67. Fall 201467 Multiplier Example: ASM Chart 01 G IDLE MUL0 01 Z MUL1 01 0C ←0, A ← P ←P ← n –1 A ←A +B, C ←C out P ←P ←P – 1 C ← 0, C || A || Q ← sr C || A || Q, Q 0 ENG241/Digital Design

68. Fall 2014ENG241/Digital Design68 Multiplier Example: Control Signal Table Block Diagram ModuleMicrooperation Control Signal Name Control Expression RegisterA:A ← 0InitializeG A ← A + BLoad MUL0 · Q0Q0 C ||A Q srC ||A QShift_decMUL1 RegisterB:B ←INLoad_BLOADB Flip-FlopC: C ← 0Clear_CIDLE · G +MUL1 C ←C out Load— RegisterQ: Q ←INLoad_QLOADQ C ||A Q ← srC ||A QShift_dec— CounterP:P ←n – 1Initialize— P ← P – 1Shift_dec— IDLE · ←

69. Fall 2014ENG241/Digital Design69  Signals are defined on a register basis  LOADQ and LOADB are external signals controlled from the system using the multiplier and will not be considered a part of this design  Note that many of the control signals are “reused” for different registers.  These control signals are the “outputs” of the control unit  With the outputs represented by the table, they can be removed from the ASM giving an ASM that represents only the sequencing (next state) behavior Multiplier Example: Control Table (continued)

70. Fall 201470 Example - Sequencing Part of ASM 0 1 IDLE MUL0 0 1 01 MUL1 10 00 G Z ENG241/Digital Design

71. Fall 2014ENG241/Digital Design71 Multiplier Example: Flip-flop per State Design Logic Diagram D C IDLE D C MUL0 D C MUL1 Initialize Clear _C Load Shift_dec Clock Z Q 0 4 1 G 2 5 4 5 1 15 DEMUX D 0 D 1 A 0 EN 2 DEMUX D 0 D 1 A 0 EN START

72. Fall 2014ENG241/Digital Design72 Example: Cont.. Sequencer and Decoder Design  First, define: States: IDLE, MUL0, MUL1 Input Signals: G, Z, Q 0 ( Q 0 affects outputs, not next state) Output Signals: Initialize, LOAD, Shift_Dec, Clear_C State Transition Diagram Output Function.  Second, find State Assignments (two bits required) We will use two state bits to encode the three state IDLE, MUL0, and MUL1.

73. Fall 2014ENG241/Digital Design73  Assuming that state variables M1 and M0 are decoded into states, the next state part of the state table is: Example: Cont.. Sequencer and Decoder Design

74. Fall 2014ENG241/Digital Design74 Example: Cont.. Sequencer and Decoder Design

75. Fall 2014ENG241/Digital Design75 Example: Cont.. Sequencer and Decoder Design  Finding the equations for M1 and M0 is easier due to the decoded states: M1 = MUL0 M0 = IDLE · G + MUL1 · Z’  Note that since there are five variables, a K-map is harder to use, so we have directly written reduced equations.  The output equations using the decoded states: Initialize = IDLE · G Load = MUL0 · Q 0 Clear_C = IDLE · G + MUL1 Shift_dec = MUL1

76. Fall 2014ENG241/Digital Design76 Sequencer and Decoder Design IDLE MUL0 MUL1 Initialize Clear_C Shift_dec M 0 Load M 1 G Z Q 0 DECODER A0 A1 0 3 2 1 D C D C START

77. Fall 2014ENG241/Digital Design77 VHDL for Binary Multiplier - 1 -- Binary Multiplier with n = 4 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity binary_multiplier is port(CLK, RESET, G, LOADB, LOADQ: in std_logic; MULT_IN: in std_logic_vector(3 downto 0); MULT_OUT: out std_logic_vector(7 downto 0)); end binary_multiplier;

78. Fall 2014ENG241/Digital Design78 VHDL for Binary Multiplier - 1 -- Binary Multiplier with n = 4 architecture sequential of binary_multiplier is type state_type is (IDLE, MUL0, MUL1); signal state, next_state: state_type; signal P: std_logic_vector(1 downto 0); signal A,B,Q: std_logic_vector(3 downto 0); signal C,Z: std_logic; begin Z <= P(1) NOR P(0); MULT_OUT <= A &Q state_register: process (CLK, RESET) …….. next_state_func: process (G, Z, state) …….. datapath_func: process (CLK) …….. end sequential;

79. Fall 2014ENG241/Digital Design79 -- state register state_register: process (CLK, RESET) begin if (RESET = '1') then state <= IDLE; elsif (CLK'event and (CLK = '1')) then state <= next_state; end if; end process; VHDL for Binary Multiplier - 2

80. Fall 2014ENG241/Digital Design80 -- next state function next_state_function: process (state, G, Z) begin case state is when IDLE => if (G = '1') then next_state <= MUL0; else next_state <= IDLE; end if; when MUL0 => next_state <= MUL1; when MUL1 => if (Z = '1') then next_state <= IDLE; else next_state <= MUL0; end if; end case; end process; VHDL for Binary Multiplier - 3

81. Fall 2014ENG241/Digital Design81 -- datapath function Datapath_func: process (CLK) variable CA: std_logic_vector (4 downto 0); begin if (CLK'event and (CLK = '1')) then if (LOADB = '1') then B <= MULT_IN; elsif (LOADQ = '1') then Q <= MULT_IN; end if; case state is when IDLE => if G = '1‘ then C <= ‘0’; A <= "0000"; P <= “11”; end if; VHDL for Binary Multiplier - 4

82. Fall 2014ENG241/Digital Design82 -- cont ….datapath function case state is ……. when MUL0 => if Q(0) = ‘1’ then CA := (‘0’ & A) + (‘0’ & B); else CA <= C & A; end if; C <= CA(4); A < CA (3 downto 0); when MUL1 => C =< ‘0’ A <= C & A(3 downto 1); Q <= A(0) & Q(3 downto 1); P = P – “01”; end case; end if; end process VHDL for Binary Multiplier - 4