SLAAC Systems Level Applications of Adaptive Computing Delivering ACS Technology to Applications DARPA/ITO Adaptive Computing Systems PI Meeting San Juan,

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Presentation transcript:

SLAAC Systems Level Applications of Adaptive Computing Delivering ACS Technology to Applications DARPA/ITO Adaptive Computing Systems PI Meeting San Juan, Puerto Rico October 6-8, 1999 Project Lead: Bob Parker Presented by: Steve Crago Information Sciences Institute

Steve Crago USC INFORMATION SCIENCES INSTITUTE Page 2 Outline l Overview l Hardware Status l “Customer” Applications n Electronic Countermeasures Analysis (ECMA) n Sonar Beamforming

Steve Crago USC INFORMATION SCIENCES INSTITUTE Page 3 SLAAC Objectives l l Define a system-level open, distributed heterogeneous adaptive computing architecture l l Design, develop and evolve scalable reference platforms implementing the adaptive systems architecture l l Validate the approach by deploying reference platforms in multiple defense application domains n n SAR ATR n n Sonar Beamforming n n ECMA n n Others

Steve Crago USC INFORMATION SCIENCES INSTITUTE Page 4 Team Members: USC/ISI (Lead), BYU, UCLA, VT, Sandia National Labs, LANL, LM-GES Significant reduction in power, weight, volume, and cost for several challenging DoD embedded applications Demonstrate 500x reduction in system volume on SAR/ATR ACS challenge Demonstrate First forward looking, 50,000 beam towed array on ACS sonar challenge Utilizing Three Phases of Adaptive Computing Components Large Current Generation FPGAs Rapid Reconfigurable and/or Fine Grain FPGAs Hybrid FPGAs Integrating Multiple Constituent Technologies Gigabit/Sec Networking Modular Adaptive Compute Modules Network Based Runtime Control Software Algorithm Analysis/ CompilationTools Developing Reference Platforms Flight Worthy Deployable System Low Cost Researchers Kit ‘97‘98‘99 Lab Demo of an ACS implemented SAR ATR algorithm Embedded SAR ATR Demo of ACS HW (Clear, 1Mpixel/s, 6TT) First Generation of Reference Platforms ‘01 Embedded SAR ATR Demo (CC&D, 1Mpixel/s, 6TT) ‘00 Embedded SAR ATR Demo (CC&D, 10Mpixel/s, 6TT) System Level Applications of Adaptive Computing

Steve Crago USC INFORMATION SCIENCES INSTITUTE Page 5 SLAAC Affiliates

Steve Crago USC INFORMATION SCIENCES INSTITUTE Page 6 SLAAC Technologies SLAAC ApplicationMapping ModuleGenerators RuntimeSystem Hardware Hosts Nodes Network T72 SLAAC is delivering ACS technology! - SLAAC, WILDFORCE, WILD-ONE,...

Steve Crago USC INFORMATION SCIENCES INSTITUTE Page 7 Technology Integration ACS technology is targeting SLAAC! SLAAC JHDL (CDs available) DebuggerEnvironments(Boardscope) ModuleGenerators (FOA compiler, DEFACTO) JBits NewChips(Virtex, ACS chips) RuntimeExtensions(Debug,DynamicReconfiguration)DesignEnvironments(Adapters,Cameron,Matlab)I/O(QC-64,Myrinet)

Steve Crago USC INFORMATION SCIENCES INSTITUTE Page 8 SLAAC Node Architecture l VHDL model available n Model Technologies n Synopsys l JHDL port coming soon… X0 IF X1X2  SRAM

Steve Crago USC INFORMATION SCIENCES INSTITUTE Page 9 SLAAC-1 Board l Simulation Environment l Drivers n Windows NT driver running n Linux driver coming soon… l Runtime system SLAAC API ( l Synthesis n Synplicity n Synopsys X0 IF X1X2 

Steve Crago USC INFORMATION SCIENCES INSTITUTE Page 10 SLAAC-1 Status l Working hardware! l Transitioned to university labs l Designs running in all FPGAs Order from

Steve Crago USC INFORMATION SCIENCES INSTITUTE Page 11 SLAAC-2 Board PowerPC Bus A X0 IF X1X2  PowerPC Bus B X0 IF X1X2  72 / 40 / 40 / l l Simulation Environment l l Drivers n n VxWorks l l Runtime system n n SLAAC API l l Synthesis n n Synplicity n n Synopsys

Steve Crago USC INFORMATION SCIENCES INSTITUTE Page 12 SLAAC-2 Status l Working hardware! l Delivered to Lockheed Martin-GES l Designs running in all FPGAs Order from