MonolithIC 3D Inc., Patents Pending MonolithIC 3D ICs November MonolithIC 3D Inc., Patents Pending

MonolithIC 3D Inc. Patents Pending 2 Monolithic 3D RC-JLT (Recessed-Channel Junction-Less Transistor )

MonolithIC 3D Inc. Patents Pending 3 Monolithic 3D IC technology is applied to producing monolithically stacked low leakage Recessed Channel Junction-Less Transistors (RC-JLTs). Junction-less (gated resistor) transistors are very simple to manufacture, and they scale easily to devices below 20nm: Bulk Device, not surface Fully Depleted channel Simple alternative to FinFET Superior contact resistance is achieved with the heavier doped top layer. The RCAT style transistor structure provides ultra-low leakage. Monolithic 3D IC provides a path to reduce logic, SOC, and memory costs without investing in expensive scaling down. Technology

RCJLT – a monolithic process flow MonolithIC 3D Inc., Patents Pending 4 Wafer, ~700µm ~100nm P- N++ N+ Using a new wafer, construct dopant regions in top ~100nm and activate at ~1000ºC Oxide

MonolithIC 3D Inc. Patents Pending 5 ~100nm P- Oxide Implant Hydrogen for Ion-Cut H+ Wafer, ~700µm N++ N+

MonolithIC 3D Inc. Patents Pending 6 ~100nm P- ~10nm H+ Oxide Hydrogen cleave plane for Ion-Cut formed in donor wafer Wafer, ~700µm N++ N+

MonolithIC 3D Inc. Patents Pending 7 ~100nm N++ N+ Oxide 1µ Top Portion of Base Wafer H+ Flip over and bond the donor wafer to the base (acceptor) wafer Base Wafer, ~700µm Donor Wafer, ~700µm P-

MonolithIC 3D Inc. Patents Pending 8 ~100nm N++ N+ Oxide 1µ Top Portion of Base Wafer Perform Ion-Cut Cleave Base Wafer ~700µm

9 ~100nm N++ N+ Oxide 1µ Top Portion of Base Wafer MonolithIC 3D Inc. Patents Pending Complete Ion-Cut Base Wafer ~700µm

10 ~100nm N++ N+ Oxide 1µ Top Portion of Base Wafer MonolithIC 3D Inc. Patents Pending Etch Isolation regions as the first step to define RCAT transistors Base Wafer ~700µm

11 ~100nm N++ N+ Oxide 1µ Top Portion of Base Wafer MonolithIC 3D Inc. Patents Pending Fill isolation regions (STI-Shallow Trench Isolation) with Oxide, and CMP Base Wafer ~700µm

12 ~100nm N++ N+ Oxide 1µ Top Portion of Base Wafer MonolithIC 3D Inc. Patents Pending Etch RCAT Gate Regions Base Wafer ~700µm Gate region

13 ~100nm N++ N+ Oxide 1µ Top Portion of Base Wafer MonolithIC 3D Inc. Patents Pending Form Gate Oxide Base Wafer ~700µm

14 ~100nm N++ N+ Oxide 1µ Top Portion of Base Wafer MonolithIC 3D Inc. Patents Pending Form Gate Electrode Base Wafer ~700µm

15 ~100nm N++ N+ Oxide 1µ Top Portion of Base Wafer MonolithIC 3D Inc. Patents Pending Add Dielectric and CMP Base Wafer ~700µm

16 ~100nm N++ N+ Oxide 1µ Top Portion of Base Wafer MonolithIC 3D Inc. Patents Pending Etch Thru-Layer-Via and RCJLT Transistor Contacts Base Wafer ~700µm

17 ~100nm N++ N+ Oxide 1µ Top Portion of Base Wafer MonolithIC 3D Inc. Patents Pending Fill in Copper Base Wafer ~700µm

18 ~100nm N++ N+ Oxide 1µ Top Portion of Base (acceptor) Wafer MonolithIC 3D Inc. Patents Pending Add more layers monolithically Base Wafer ~700µm Oxide ~100nm N++ N+

MonolithIC 3D Inc. Patents Pending 19 2x lower power 2x smaller silicon area 4x smaller footprint Layer to layer interconnect density at close to full lithographic resolution and alignment Performance of single crystal silicon transistors on all layers in the 3D IC Scalable: scales naturally with equipment capability Forestalls next gen litho-tool risk Also useful as Anti-Fuse FPGA programming transistors: programmable interconnect is 10x-50x smaller & lower power than SRAM FPGA Base logic circuits could be UT-BBOX, FinFET, or JLT CMOS logic devices Benefits for RCJLT

MonolithIC 3D Inc. Patents Pending 20 Create a layer of Recessed Channel Junction-Less Transistors (RC-JLTs), a junction-less version of the RCAT used in DRAMs, by activating dopants at ~1000°C before wafer bonding to the CMOS substrate and cleaving, thereby leaving a very thin doped stack layer from which transistors are completed, utilizing less than 400°C etch and deposition processes. RC-JLT flow: Summary