ECE 477 DESIGN REVIEW FEST – FALL 2011

OUTLINE  Project overview  Project-specific success criteria  Block diagram  Component selection rationale  Packaging design  Schematic and theory of operation  PCB layout  Software design/development status  Project completion timeline  Questions/discussion

PROJECT OVERVIEW  Automated system for testing speakerphones  Delivers test signals pre-recorded audio  Used to determine time delay frequency response  Records audio output from DUT

PSSC  An ability to measure time delay response between project’s components; the playback device, the telephone line simulator, the DUT which is the speakerphone, and the receiving device.  An ability to determine the frequency response of the DUT.  An ability to “play back” sound files.  An ability to record audio and write it to non-volatile (removable) memory.  An ability to perform duplex testing of recording data and playing back data.

BLOCK DIAGRAM

COMPONENT SELECTION RATIONALE  TMS320F MCU 80 pin count, 128KB on-chip Flash ANSI C language 60 MHz 2 - SPI, 1- SCI, 1 – I 2 C 14 PWM and 16 ATD

COMPONENT SELECTION RATIONALE  TLV320AIC23 Audio Codec 8 – 96 KHz sampling up to 24-bit depth Stereo Channel

COMPONENT SELECTION RATIONALE  LCD – SCI/SPI interface Programmable baud rate 20 x 4

COMPONENTS PROVIDED

PACKAGING DESIGN  Back Power switch Reset button Power jack Power LED  Side SD Card RJ11

PROJECT PACKAGING  Front Microphone XLR ¼” Speaker  TOP LCD 4 Push Buttons

Front Left Top

THEORY OF OPERATION Power Management Power rails of 3.3 V and 5.0 V needed. Two voltage regulators will be used for getting the desired power rails.

POWER SCHEMATIC

THEORY OF OPERATION SD Card Operating Voltage - 3.3V Interfaced using SPI module. Run at 15 Mhz (Maximum supported by SPI moudle) Will be used to read and write audio files.

SD CARD SCHEMATIC

THEORY OF OPERATION LCD Operating Voltage – 5.0V Interfaced using SCI module. Run at 9600 Baud rate Will be used to implement a simple user interface. 20 x 4

LCD SCHEMATIC

SCHEMATIC THEORY OF OPERATION  MCU SPI

SCHEMATIC THEORY OF OPERATION  MCU I 2 C – Used to program the codec

SCHEMATIC THEORY OF OPERATION

MAIN (MCU AND POWER)  MAIN PCB Includes: 5V and 3.3V Regulators (LT1086) TI Microcontroller (TMS320F28035) Transceiver (MAX3221) Digital Isolator (ISO7221A) 14-pin Header SD Card Header (M11) JTAG Power Jack “Wall wart”

MCU AND POWER

CODEC (AND OTHER)  CODEC PCB Includes: Codec (TLV320AIC23B) 3.5mm Audio Jacks (Microphone & Speaker) Data Access Arrangement device (CH1840) Microphone Preamplifier (MAX4063) Simple 6-pin RJ11 Jack Potentiometer 14-pin Header 5V and 3.3V Regulators (LT1086)

CODEC AND OTHER

PIN ASSIGNMENT GPIO PINSMux 1Mux 2Mux 3Mux 4 GPIO Name GPIO00EPWM1A GPIO01EPWM1B COMP1OUT GPIO02EPWM2A GPIO03EPWM2BSPISOMIACOMP2OUT GPIO04EPWM3A OP3* GPIO05EPWM3BSPISIMOAECAP1 SPIA_WP* GPIO06EPWM4AEPWMSYNCIEPWMSYNCO GPIO07EPWM4BSCIRXDA GPIO08EPWM5A ADCSOCAO' GPIO09EPWM5BLINTXAHRCAP1 GPIO10EPWM6A ADCSOCBO' GPIO11EPWM6BLINRXAHRCAP2 SPIA_CD* GPIO12TZ1'SCITXDASPISIMOB GPIO13TZ2'SPISOMIB DATA/VOICE* GPIO14TZ3'LINTXASPICLKB RUN/STOP* GPIO15TZ1'LINRXASPISTEB' GPIO16SPISIMOATZ2' GPIO17SPISOMIATZ3'

PIN ASSIGNMENT GPIO PINSMux 1Mux 2Mux 3Mux 4 GPIO Name GPIO18SPICLKALINTXAXCLKOUT GPIO19XCLKINSPISTEA'LINRXAECAP1 GPIO20EQEP1A COMP1OUT GPIO21EQEP1B COMP2OUT OFF_HOOK* GPIO22EQEP1S LINTXA GPIO23EQEP1ILINRXA GPIO24ECAP1 SPISIMOB GPIO25SPISOMIB GPIO26HRCAP1SPICLKB GPIO27HRCAP2SPISTEB' GPIO28SCIRXDASDAATZ2' GPIO29SCITXDASCLATZ3' GPIO30CANRXA GPIO31CANTXA GPIO32SDAAEPWMSYNCIADCSOCAO' GPIO33SCLAEPWMSYNCOADCSOCBO' GPIO34COMP2OUTCOMPT3OUT GPIO35TDI

PIN ASSIGNMENT GPIO PINSMux 1Mux 2Mux 3Mux 4 GPIO Name GPIO36TMS GPIO37TDO GPIO38TCKXCLKIN GPIO39 OP2* GPIO40EPWM7A OP0* GPIO41EPWM7B OP1* GPIO42COMP1OUT GPIO43COMP2OUT GPIO44

PIN ASSIGNMENT ADCComparatorDigital Input ADCINA7 ADCINA6COMP3AAIO6 ADCINA5 ADCINA4COMP2AAIO4 ADCINA3 ADCINA2COMP1AAIO2 ADCINA1 ADCINA0 ADCINB7 ADCINB6COMP3BAIO14 ADCINB5 ADCINB4COMP2BAIO12 ADCINB3 ADCINB2COMP1BAIO10 ADCINB1 ADCINB0

SOFTWARE DESIGN DEVELOPMENT STATUS  Interrupt-driven software  Interrupt generated by Timer module for accurate task transition Each interrupt causes MCU to switch task and spoon-feed necessary modules with data (SPI, SCI, I 2 C, etc.) Buttons also generate interrupt  Same repetitive tasks until test is stopped or SD card is full  Remaining CPU time for signal processing math

SOFTWARE DESIGN DEVELOPMENT STATUS

1.Out-of-reset Display menu Check SD card status Display test options 2.Begin test Measure time delay Measure frequency response Any other pre-programmed tests 3.Free-run test until SD card is full

TIMELINE *DR = Design Review WeekExpected Completion (Week) FatFS (FAT32)DR  DR + 4 FFT + Auto CorrelationDR + 2  DR + 6 Wrap Up ( Processor Time Allocation ) DR + 4  DR + 6 Interrupt, SCI, Codec(I 2 C, SPI, and Timer) DR Wave File HeaderDR

QUESTIONS Please Don’t ask any…