2. ECE 477 Design Review Team 3  Fall 2007 Steven Kingsley (Analog) Roy Scheck (Leader) Tony Liechty (Digital) Charles Lan (Software)

3. Outline Project overviewProject overview Project-specific success criteriaProject-specific success criteria Block diagramBlock diagram Component selection rationaleComponent selection rationale Packaging designPackaging design Schematic and theory of operationSchematic and theory of operation PCB layoutPCB layout Software design/development statusSoftware design/development status Project completion timelineProject completion timeline Questions / discussionQuestions / discussion

4. Project Overview Allows a single note instrument to be used as a MIDI instrumentAllows a single note instrument to be used as a MIDI instrument Ability to tune the instrument for more accurate MIDI conversionAbility to tune the instrument for more accurate MIDI conversion MIDI is an audio standardMIDI is an audio standard Software allows real time composition of music from MIDISoftware allows real time composition of music from MIDI

5. Project-Specific Success Criteria 1.Ability to detect the fundamental frequency of a note from a single note instrument through an analog microphone. 2.Ability to determine/guess the “closest note” being played based on the fundamental frequency detected (in 1 above). 3.An ability to calculate “how far off” (out-of-tune) the note being played is relative to the intended “nearest note” (determined in 2 above). 4.Ability to communicate note information to a computer. 5.Ability to display note detection/operational status using an LCD display.

6. Block Diagram PreAmp Filter Microphone DSP LCD USB interface ATD Volume Control Parallel GPIO 2 SPI 7 I2C 4 Volume Knob 2 PWM GPIO

7. Component Selection Rationale DSP requirementsDSP requirements 1 ATD converter1 ATD converter At least 8 bits for sufficient resolutionAt least 8 bits for sufficient resolution SPI interface for SPI to USB controllerSPI interface for SPI to USB controller I2C for digital potentiometerI2C for digital potentiometer PWM for analog filterPWM for analog filter 7 GPIO pins for parallel LCD interface7 GPIO pins for parallel LCD interface ~1200 bytes of RAM for sampling~1200 bytes of RAM for sampling 10Mhz Clock for proper resolution10Mhz Clock for proper resolution

8. Component Selection Rationale Possible DSPsPossible DSPs –Freescale 56F8014 16 Kbyte flash, 4 Kbyte RAM16 Kbyte flash, 4 Kbyte RAM 32 Mhz Clock, 32 pins32 Mhz Clock, 32 pins $3.15 in 1,000 quantities$3.15 in 1,000 quantities –Atmel AT32UC3B164 64 Kbyte flash, 16 Kbyte RAM64 Kbyte flash, 16 Kbyte RAM 90 Mhz Clock, 48 pins90 Mhz Clock, 48 pins $4.66 in 10,000 quantities$4.66 in 10,000 quantities NewerNewer

9. Component Selection Rationale DSPDSP –Freescale 56F8014 ($3.15) 32 total pins32 total pins Two 12-bit ATDsTwo 12-bit ATDs SPI, SCI, I2C, PWMSPI, SCI, I2C, PWM 21 GPIO21 GPIO 16 Kb flash, 4 Kb RAM16 Kb flash, 4 Kb RAM 32 Mhz Clock32 Mhz Clock 4 pin JTAG/OnCE Interface for programming4 pin JTAG/OnCE Interface for programming

10. Component Selection Rationale USB ControllerUSB Controller –MAX3421E ($2.65) USB Peripheral Controller with SPI InterfaceUSB Peripheral Controller with SPI Interface Allows any microcontroller with SPI to be connected over USBAllows any microcontroller with SPI to be connected over USB 2 GPIO for Volume Knob2 GPIO for Volume Knob –Easier Routing –Accessed through SPI

11. Component Selection Rationale LCDLCD –CFAH1602B-YTI-JP 4 bit parallel interface (4 pins)4 bit parallel interface (4 pins) 3 bit functionality (3 pins)3 bit functionality (3 pins) Power consumptionPower consumption –1.5 ma for LCD –150 ma for Backlight

12. Packaging Design Form FactorForm Factor –Small for mobility –Sloped panel for easy viewing and better microphone reception Packaging FeaturesPackaging Features –LCD display of Note Information and Volume –Incoming Signal Amplifier (Rotary Knob) –Internal Microphone –USB Interface (Female “B” Adapter)

13. Packaging Design Hammond 1456CE2Hammond 1456CE2

14. Schematic/Theory of Operation PreAmp Filter Microphone DSP LCD USB interface ATD Volume Control D+ D- Parallel GPIO 2 SPI 7 I2C 4 Volume Knob 2 PWM GPIO

15. Schematic/Theory of Operation Power Supplies (3.3V, 1 Amp)Power Supplies (3.3V, 1 Amp) –Separate Analog and Digital supplies

16. Schematic/Theory of Operation AnalogAnalog –Amplify and Bias at 1.65V –Filter 10 mV -10 mV 0 V 3 V 0 V

17. Schematic/Theory of Operation Filter Digital Potentiometer Amplifier

18. Schematic/Theory of Operation Digital Potentiometer Amplifier DSP ATD GPIO SPI I2C PWM

19. Schematic/Theory of Operation Amplifier DSP ATD GPIO SPI I2C PWM Filter

20. Schematic/Theory of Operation USB interface D+D- LCD Parallel OnCE Volume Control Filter Clock Interrupt DSP

21. Schematic/Theory of Operation DSP ATD GPIO SPI I2C PWM SPI To USB

22. Schematic/Theory of Operation DSP ATD GPIO SPI I2C PWM Ground Header

23. PCB Layout General Design ConsiderationsGeneral Design Considerations Specific Design ConsiderationsSpecific Design Considerations –Power Supply –Analog –Digital

24. PCB Layout General Design ConsiderationsGeneral Design Considerations –Overall low power consumption General trace width of 10 milsGeneral trace width of 10 mils –Separate Analog and Digital systems –Minimize trace length –Minimize angles

25. PCB Layout Power Supply Design ConsiderationsPower Supply Design Considerations –Separate Analog and Digital Separate GroundsSeparate Grounds –5 V Unregulated Supply Trace width of 80 milsTrace width of 80 mils –3.3 V Regulated Supply Trace width of 70 milsTrace width of 70 mils –Bypass Capacitors Placed directly beneath Voltage RegulatorsPlaced directly beneath Voltage Regulators

26. PCB Layout Analog Design ConsiderationsAnalog Design Considerations –High sensitivity Ground shieldingGround shielding Copper PourCopper Pour –Microphone Minimize leadsMinimize leads –Bypass Capacitors Placed directly beneath respective ICPlaced directly beneath respective IC

27. PCB Layout Digital Design ConsiderationsDigital Design Considerations –Bypass Capacitors Placed directly beneath MicrocontrollerPlaced directly beneath Microcontroller –Bulk Capacitors Placed further from MicrocontrollerPlaced further from Microcontroller –General Purpose I/O Pins Assigned to corresponding side to minimize lengthAssigned to corresponding side to minimize length

36. Software Design/Development Status Three options for developmentThree options for development –JTAG/OnCE Easy to debugEasy to debug Costly Development boardCostly Development board –SCI serial bootloader Frees up more pinsFrees up more pins Addition of level translators and RS232 implementationAddition of level translators and RS232 implementation –Bulk device programmer Hard to debug after packagingHard to debug after packaging Easy to program multiple chipsEasy to program multiple chips

37. Software Design/Development Status Frequency DetectionFrequency Detection –Zero-crossings (currently favored approach) –Peak counting –Hybrid model –Shift/Compare Simulations run in C++ using DirectSoundSimulations run in C++ using DirectSound

38. Project Completion Timeline Week #12345678910111213141516 PCB Assembly of PCB Software Packaging Testing Documentation Research Schematic Project Finalization Thanksgiving Current Week

39. Questions / Discussion