1. ECE 477 Design Review Team 4  Spring 2008 Zach Dicklin Amy Ritter Ian Bacon Eric Yee

2. Outline Project overviewProject overview Project-specific success criteriaProject-specific success criteria Block diagramBlock diagram Component selection rationaleComponent selection rationale Packaging designPackaging design Schematic and theory of operationSchematic and theory of operation PCB layoutPCB layout Software design/development statusSoftware design/development status Project completion timelineProject completion timeline Questions / discussionQuestions / discussion

3. Project Overview RFID DigiJocks DigiJock shoppers also like to shop at… AD Targeting ads… Reaching demographics… The future of advertising!

4. Project-Specific Success Criteria RFID DigiJocks Decode a valid shopper RFID tag.Decode a valid shopper RFID tag.

5. Project-Specific Success Criteria Retrieve shopper’s characteristics from a database indexed by decoded ID.Retrieve shopper’s characteristics from a database indexed by decoded ID. RFID DigiJocks What does this DigiJock like?

6. Project-Specific Success Criteria Load “general” and targeted advertisements from a database.Load “general” and targeted advertisements from a database. RFID DigiJocks Where is this ad?

7. Project-Specific Success Criteria Display targeted advertisement images on a local LCD in response to current shopper’s ID.Display targeted advertisement images on a local LCD in response to current shopper’s ID. RFID DigiJocks AD

8. Project-Specific Success Criteria Display “general” advertisement images on a local LCD when valid RFID tag is not detected.Display “general” advertisement images on a local LCD when valid RFID tag is not detected. RFID DigiJocks HI

9. Block Diagram Microcontroller (MC9S12NE64) Level Shifter (Max3322) LCD Controller (SLCD) RFID Reader (TRRO1OEM) RFID tags 2 CLOCK 1 Push Button SD Card Reader (BOB-00204) RJ-45 4 2 4 7 2 1 Voltage Regulator 3.3V Microcontroller (MC9S12NE64) Level Shifter (Max3322) LCD Controller (SLCD) RFID Reader (TRRO1OEM) RFID tags 2 CLOCK 1 Push Button SD Card Reader (BOB-00204) RJ-45 4 2 4 7 2 1 Voltage Regulator 3.3V SCI SPI Ethernet SCI SPI Ethernet

10. Component Selection Rationale Agatha’s Major ComponentsAgatha’s Major Components –Microcontroller MC9S12NE64 Freescale FREE + DevKit On board 2 Channels

11. Component Selection Rationale Agatha’s Major ComponentsAgatha’s Major Components –RFID Reader TRR01OEM Up to 28.25 inches* 6 x 6 x 1.5 cm YES YES (round / 18” diameter) $78.00 *tag dependent **includes license fee

12. Agatha’s Major ComponentsAgatha’s Major Components –Display driver $429 Component Selection Rationale *includes external RAM SLCD SCI $240 (discounted)

13. Packaging Design Outer KioskOuter Kiosk –5.7” LCD Display –5’ for eye-level viewing –Wood construction –Weighted

14. Packaging Design Inner KioskInner Kiosk –Circuitry on floor –Power/Ethernet –LCD Screen –RS-232 runs 15’ to RFID reader

15. Packaging Design 120 12 Microprocessor (HC9S12NE64) 31 3.8 24 Serial Port 15.9 Ethernet 31 Level shifter 3.8 I/O Header 40 14 10 2.5 Serial Port 31 10 SPI Header 103 (Dimensions in mm)

16. Schematic/Theory of Operation Main functionsMain functions –Read RFID Tags –Choose a display image –Retrieve image data from updatable SD card –Communicate / update data with Ethernet –Send image data to LCD screen –User interaction with display

17. Schematic/Theory of Operation Basic Power RequirementsBasic Power Requirements –All components run at 3.3V –On board voltage regulator –Microcontroller voltage regulator

18. Schematic/Theory of Operation MICRO I/O & USER INPUT CLOCKING BDM SCI SERIAL SPI Pinout ETHERNET POWER

19. HEADER Power/Ground header for 5V Wall-wart DIODE/FUSE REGULATOR 278R33 - 3.3V regulator Diode/Fuse for protection

20. Schematic/Theory of Operation MICRO I/O & USER INPUT CLOCKING BDM SCI SERIAL SPI Pinout ETHERNET POWER MICRO

21. MC9S12NE64 I/O SCISPI ETHERNET Decoupling Caps Interfacing 3.3 Voltage Rail Ground Rail 3.3 Voltage Rail Ground Rail DECOUPLING CAPS D CAP CLOCKING BDM

22. Schematic/Theory of Operation MICRO I/O & USER INPUT CLOCKING BDM SCI SERIAL SPI Pinout ETHERNET POWER ETHERNET

23. RJ-45 Connector RJ-45 DECOUPLING CAPS PULL UP Pull Up Resistors Freescale’s suggested layout Decoupling caps 3.3 Voltage Rail

24. Schematic/Theory of Operation MICRO I/O & USER INPUT CLOCKING BDM SCI SERIAL SPI Pinout ETHERNET POWER CLOCKING BDM

25. CLOCKING BDM Freescale’s suggested layout 3.3 Voltage Rail Ground Rail HEADER BDM with external reset switch Clocking - 25MHz RESET SWITCH 25 MHz Oscillator CAP / RES network

26. Schematic/Theory of Operation MICRO I/O & USER INPUT CLOCKING BDM SCI SERIAL SPI Pinout ETHERNET POWER SCI SERIAL

27. Both SCI ports Pinned out HEADER Level Shifter MAX3222 Level Shifter CAP / RES NETWORK Suggested Layout SERIAL PORTS SLCD and RFID connections

28. Schematic/Theory of Operation MICRO I/O & USER INPUT CLOCKING BDM SCI SERIAL SPI Pinout ETHERNET POWER

29. SPI Pinout HEADER 3.3 Voltage Rail Ground Rail SPI interfaces with SD Card Reader Status LED’s using PG port GPIO STATUS LED’S 3.3 Voltage Rail

30. Schematic/Theory of Operation MICRO I/O & USER INPUT CLOCKING BDM SCI SERIAL SPI Pinout ETHERNET POWER I/O & USER INPUT

31. 3.3 Voltage Rail I/O & USER INPUT I/O Header Optical Isolator GPIO Header 3.3 V Ground Header for Push Button OPTICAL ISOLATOR PUSH BUTTON

32. Schematic/Theory of Operation MICRO I/O & USER INPUT CLOCKING BDM SCI SERIAL SPI Pinout ETHERNET POWER

33. PCB Layout Main considerationsMain considerations –Parallel power and ground rails –Decoupling Capacitors near components –Transmit and Receive lines uninterrupted –Ethernet / Clocking circuits isolated

34. POWER PCB Layout MICRO I/O & USER INPUT CLOCKING BDM SCI SERIAL SPI ETHER- NET POWER

35. PCB Layout Main power and ground rails parallel Minimal current looping Trace width of 60mil POWER

36. PCB Layout Main power and ground rails parallel Minimal current looping Trace width of 60mil POWER Header easily accessed on edge HEADER DIODE& FUSE Diode / Fuse protection REGULATOR On board regulator Status LED’s STATUS LEDs

37. PCB Layout MICRO I/O & USER INPUT CLOCKING BDM SCI SERIAL SPI ETHER- NET POWER

38. MICRO Clocking/BDM Ethernet Decoupling Caps CLOCKING BDM ETHERNET ETHERNET CAPS CAP CAPS

39. PCB Layout MICRO I/O & USER INPUT CLOCKING BDM SCI SERIAL SPI ETHER- NET POWER

40. ETHER- NET RJ-45 on edge RJ-45 RESIST / CAPS Clear, short path for traces Resist and Caps

41. PCB Layout MICRO I/O & USER INPUT CLOCKING BDM SCI SERIAL SPI ETHER- NET POWER

42. CLOCKING BDM SPI SPI for SD pinned out CLOCKING CAPS Clocking isolated OSC BDM pinned out BDM HEADER SWITCH

43. PCB Layout MICRO I/O & USER INPUT CLOCKING BDM SCI SERIAL SPI ETHER- NET POWER

44. SCI SERIAL SCI Traces Layer shifter on bottom LEVEL SHIFTER HEADER SCI Pinout Ports on edge PORT

45. PCB Layout MICRO I/O & USER INPUT CLOCKING BDM SCI SERIAL SPI ETHER- NET POWER

46. I/O & USER INPUT Extra I/O Pinouts PORT Optical Isolator OPTICAL ISOLATOR PUSH BUTTON HEADER External User Input

47. PCB Layout MICRO I/O & USER INPUT CLOCKING BDM SCI SERIAL SPI ETHER- NET POWER

48. Software Design/Development Status Basic interfacing of peripheralsBasic interfacing of peripherals –SCI, SPI, GPIO RFID systemRFID system –Antenna and reader communicating SD CardSD Card –Attempting card communication LCD displayLCD display –Transferring of bitmaps

49. Project Completion Timeline TASKDESCRIPTIONWeek 9Week 10Week 11Week 12Week 13Week 14Week 15 Hardware Revise Schematic Design Revise PCB Layout Component Soldering Board Testing Software Initial Peripheral Communication SLCD Communication SLCD Image display RFID Communication RFID tag reading SPI/SD card read and write Image Display Algorithm Ethernet Initialization FAT File System Design Update Files through Ethernet Packaging Kiosk Prototyping Kiosk Construction Hardware Integration Documentation User Manual Final Presentation/Documentation

50. Questions / Discussion

51. Schematic/Theory of Operation MICRO I/O & USER INPUT CLOCKING BDM SCI SERIAL SPI Pinout ETHERNET POWER

53. PCB Layout MICRO I/O & USER INPUT CLOCKING BDM SCI SERIAL SPI ETHER- NET POWER