ELEN 468 Lecture 111 ELEN 468 Advanced Logic Design Lecture 11 Switch Level Models

ELEN 468 Lecture 112 MOS Transistor Technology p substrate n well nnpp source drain gate g d s s d g

ELEN 468 Lecture 113 Switch Level Models nmoscontrol Input01xz 0z0LL 1z1HH xzxxx zzzzz pmoscontrol Input01xz 00zLL 11zHH xxzxx zzzzz L => 0 or z, H => 1 or z

ELEN 468 Lecture 114 Static CMOS Circuits module cmos_inverter ( out, in ); output out; input in; supply0 GND; supply1 PWR; pmos ( out, PWR, in ); nmos ( out, GND, in ); endmodule module cmos_inverter ( out, in ); output out; input in; supply0 GND; supply1 PWR; pmos ( out, PWR, in ); nmos ( out, GND, in ); endmodule d inout V dd drain source gate

ELEN 468 Lecture 115 Switch Level NAND Gate module nand_2 ( Y, A, B ); output Y; input A, B; supply0 GND; supply1 PWR; wire w; pmos ( Y, PWR, A ); pmos ( Y, PWR, B ); nmos ( Y, w, A ); nmos ( w, GND, B ); endmodule module nand_2 ( Y, A, B ); output Y; input A, B; supply0 GND; supply1 PWR; wire w; pmos ( Y, PWR, A ); pmos ( Y, PWR, B ); nmos ( Y, w, A ); nmos ( w, GND, B ); endmodule Y V dd A A B B

ELEN 468 Lecture 116 Pull Gates module nmos_nand_2 ( Y, A, B ); output Y; input A, B; supply0 GND; tri w; pullup ( Y ); nmos ( Y, w, A ); nmos ( w, GND, B ); endmodule module nmos_nand_2 ( Y, A, B ); output Y; input A, B; supply0 GND; tri w; pullup ( Y ); nmos ( Y, w, A ); nmos ( w, GND, B ); endmodule Y V dd A B Y A B Enhancement/Depletion mode

ELEN 468 Lecture 117 CMOS Transmission Gates module Tgate ( in, out, n_enable, p_enable ); input in, n_enable, p_enable; output out; pmos ( out, in, p_enable ); nmos ( out, in, n_enable ); endmodule module Tgate ( in, out, n_enable, p_enable ); input in, n_enable, p_enable; output out; pmos ( out, in, p_enable ); nmos ( out, in, n_enable ); endmodule inout p_enable n_enable

ELEN 468 Lecture 118 Bi-directional Gates trantranif0tranif1 input or inout output or inout Verilog primitives

ELEN 468 Lecture 119 Assign Drive Strengths nand ( pull1, strong0 ) G1( Y, A, B ); wire ( pull0, weak1 ) A_wire = net1 || net2; assign ( pull1, weak0 ) A_net = reg_b; nand ( pull1, strong0 ) G1( Y, A, B ); wire ( pull0, weak1 ) A_wire = net1 || net2; assign ( pull1, weak0 ) A_net = reg_b; Drive strength is specified through an unordered pair one value from { supply0, strong0, pull0, weak0, highz0 } the other from { supply1, strong1, pull1, weak1, highz1 } Only scalar nets may receive strength assignment When a tri0 or tri1 net is not driven, it is pulled to indicated logic value with strength of pull0 or pull1 The trireg net models capacitance holds a charge after the drivers are removed, the net has a charge strength of small, medium(default) or large capacitor

ELEN 468 Lecture 1110 Signal Strength Levels Su0 St0 Pu0 La0 We0 Me0 Sm0 HiZ0 Su1 St1 Pu1 La1 We1 Me1 Sm1 HiZ1 Supply Drive Strong Drive Pull Drive Large Capacitor Weak Drive Medium Capacitor Weak Capacitor High Impedance Signal strength – signal’s ability to act as a logic driver determining the resultant logic value on a net Signal contention between multiple drivers of nets Charge distribution between nodes in a circuit Default – strong drive Capacitive strengths may be assigned only to trireg nets

ELEN 468 Lecture 1111 StL PuH Ambiguous Control Su0 St0 Pu0 La0 We0 Me0 Sm0 HiZ0 Su1 St1 Pu1 La1 We1 Me1 Sm1 HiZ1 x bufif0 St0 x bufif0 Pu1

ELEN 468 Lecture 1112 Strength Reduction Dependence of output strength on input strength Combinational and pull gate – NO, except 3-state gates Transistor switch and bi-directional gates – YES In general, output strength <= input strength

ELEN 468 Lecture 1113 Transistor Switch and Bi-directional Gate Transistor switch nmos, pmos, cmos Bi-directional gate tran, tranif0, tranif1 If input ( supply0 or supply1 ) Output ( strong0, strong1 ) Otherwise Output strength = input strength

ELEN 468 Lecture 1114 Resistive MOS Devices rpmos, rnmos, rcmos, rtran, rtranif0, rtranif1 Su0 St0 Pu0 La0 We0 Me0 Sm0 HiZ0 Su1 St1 Pu1 La1 We1 Me1 Sm1 HiZ1 Supply Drive Strong Drive Pull Drive Large Capacitor Weak Drive Medium Capacitor Weak Capacitor High Impedance

ELEN 468 Lecture 1115 Example of Resistive Device module inverterA ( out, r_out, in, ena ); output out, r_out; input in, ena; supply1 Vdd; supply0 Gnd; pullup ( out ); nmos ( out, Gnd, in ); rnmos ( r_out, out, ena ); endmodule module inverterA ( out, r_out, in, ena ); output out, r_out; input in, ena; supply1 Vdd; supply0 Gnd; pullup ( out ); nmos ( out, Gnd, in ); rnmos ( r_out, out, ena ); endmodule in out r_out ena Vdd Figure 11.16, page

ELEN 468 Lecture 1116 Signal Contention: Known Strength and Known Value Signal with greater strength dominates Same strength, different logic values wand -> and, wor -> or Otherwise -> x driver1 driver2 We0 Pu1

ELEN 468 Lecture 1117 Example: Same Strength, Different Logic Value Su0 St0 Pu0 La0 We0 Me0 Sm0 HiZ0 Su1 St1 Pu1 La1 We1 Me1 Sm1 HiZ1 driver1 driver2 St0 St1 StX

ELEN 468 Lecture 1118 Ambiguous Strength, Known Value Rule 1: Include strengths of ambiguous signal that greater than strength of unambiguous signal Rule 2: Omit strengths of ambiguous signal <= strength of unambiguous signal, except Rule 3 Rule 3: If unambiguous and ambiguous signals have different values, take strengths range from Rule1 to strength of unambiguous signal

ELEN 468 Lecture 1119 Example of Rule 1 Su1 St1 Pu1 La1 We1 Me1 Sm1 HiZ1 Su1 St1 Pu1 La1 We1 Me1 Sm1 HiZ1 Su0 St0 Pu0 La0 We0 Me0 Sm0 HiZ0 signal1signal2 Su1 St1 Pu1 La1 We1 Me1 Sm1 HiZ1 Su0 St0 Pu0 La0 We0 Me0 Sm0 HiZ0 result Rule 1: Include strengths of ambiguous signal that greater than strength of unambiguous signal

ELEN 468 Lecture 1120 Example of Rule 2 Su1 St1 Pu1 La1 We1 Me1 Sm1 HiZ1 Su0 St0 Pu0 La0 We0 Me0 Sm0 HiZ0 signal1signal2 Su1 St1 Pu1 La1 We1 Me1 Sm1 HiZ1 Su0 St0 Pu0 La0 We0 Me0 Sm0 HiZ0 result Su0 St0 Pu0 La0 We0 Me0 Sm0 HiZ0 Rule 2: Omit strengths of ambiguous signal <= strength of unambiguous signal, except Rule 3

ELEN 468 Lecture 1121 Example of Rule 3 Su1 St1 Pu1 La1 We1 Me1 Sm1 HiZ1 signal2 Su1 St1 Pu1 La1 We1 Me1 Sm1 HiZ1 Su0 St0 Pu0 La0 We0 Me0 Sm0 HiZ0 result signal1 Su0 St0 Pu0 La0 We0 Me0 Sm0 HiZ0 Rule 3: If unambiguous and ambiguous signals have different values, take strengths range from Rule1 to strength of unambiguous signal

ELEN 468 Lecture 1122 Ambiguous Strengths, Ambiguous Values Su0 St0 Pu0 La0 We0 Me0 Sm0 HiZ0 Su1 St1 Pu1 La1 We1 Me1 Sm1 HiZ1 x x Pu0 We1 WeH PuL 53X Su0 St0 Pu0 La0 We0 Me0 Sm0 HiZ0 Su1 St1 Pu1 La1 We1 Me1 Sm1 HiZ1 5 3

ELEN 468 Lecture 1123 Signal Strengths for Wired Logic Su1 St1 Pu1 La1 We1 Me1 Sm1 HiZ1 signal2 Su1 St1 Pu1 La1 We1 Me1 Sm1 HiZ1 Su0 St0 Pu0 La0 We0 Me0 Sm0 HiZ0 wor signal1 Su0 St0 Pu0 La0 We0 Me0 Sm0 HiZ0 wand Su0 St0 Pu0 La0 We0 Me0 Sm0 HiZ0