Digital Integrated Circuits A Design Perspective EE141 Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The Inverter Revised from Digital Integrated Circuits, © Jan M. Rabaey el, 2003

The CMOS Inverter: nucleus of digital circuits out C L DD

Inverter: First-Order DC Analysis DD in out R n p Voltage swing is equal to Vdd, so high noise margin Logic level does not depend on sizes, so can be minimum size (ratioless logic style) In steady state, a path exists with finite resistance exists between output to either Vdd or Gnd, which gives low output impedance. So less sensitive to noise and disturbances. Gate current equal to 0 In steady state, no direct path exists between Vdd and Gnd, thus no static power consumption = = VOL = 0 VOH = VDD

CMOS Inverter: Transient Response pHL = f(R on .C L ) = 0.69 R C DD DD R p V out V out C L C L R n V V V V in DD in DD (a) Low-to-high (b) High-to-low

Voltage Transfer Characteristic

PMOS Load Lines V = V +V I = - I V I V I =-2.5 =-1 V I =0 =1.5 V I =0 DD +V GSp I Dn = - I Dp out DSp V out I Dn V DSp I Dp GSp =-2.5 =-1 V DSp I Dn in =0 =1.5 V out I Dn in =0 =1.5 V in = V DD +V GSp I Dn = - I Dp V out = V DD +V DSp

CMOS Inverter Load Characteristics All operating points are located either high or low output levels (two ends) Very narrow transient zone, thus high gain in transient Transient zone

CMOS Inverter VTC Switching threshold Vm where Vin=Vout

A unified model for manual analysis of short-channel devices G B

Vm as a function of Transistor Ratio

Vm as a function of Transistor Ratio

Vm as a function of Transistor Ratio 10 1 0.8 0.9 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 M V (V) W p /W n Computed to be 3.5 Versus 3.4 from simulation Vm relatively insensitive to device ratio change

Minimum-size inverter out C L DD 9λ / 2 λ 2 λ= technology length 3λ / 2 λ

Definition of VIH and VIL Slope = -1 OL OH out V “ 1 ” OH V IH Undefined Region V IL “ ” V OL

Definition of Noise Margins "1" V OH Noise margin high NM H V IH Undefined Region NM V L Noise margin low IL V OL "0" Gate Output Gate Input

Determining VIH and VIL A simplified approach using Piece-wise linear approximation V OH OL in out M IL IH The slope equal to the gain at Vm

Computing Inverter Gain Channel length modulation effect has to be included.

Inverter Gain Assume W/L=1.5 for NMOS and 3.4*1.5 for PMOS, g=-27.5 Vil=1.2, Vih=1.3, NM=1.2 (Simulation gives NM=1.0)

Simulated VTC

Gain as a function of VDD Gain g at threshold voltage increases with reduced VDD (smaller Vm)! Gain=-1 Why not low power supply voltage: because of delay, sensitivity, signal swing and noise