Switch Logic EE141

What is a transistor? An MOS Transistor A Switch EE141

Switch Model of MOS Transistor EE141

NMOS and PMOS NMOS transistor PMOS transistor EE141

The CMOS Inverter: A First Glance out C L DD EE141

CMOS Inverter N Well V DD PMOS 2l Contacts Out In Metal 1 Polysilicon NMOS GND EE141

Two Inverters Share power and ground Abut cells Connect in Metal EE141

CMOS Inverter First-Order DC Analysis DD in 5 out R n p VOL = 0 VOH = VDD VM = f(Rn, Rp) EE141

CMOS Inverter: Transient Response DD DD t pHL = f(R on .C L ) = 0.69 R C R p V out V out C L C L R n V 5 V 5 V in in DD (a) Low-to-high (b) High-to-low EE141

Simulated VTC EE141

Inverter Chain In Out CL If CL is given: How many stages are needed to minimize the delay? How to size the inverters? May need some additional constraints. EE141

Inverter Delay Minimum length devices, L=0.25mm Assume that for WP = 2WN =2W same pull-up and pull-down currents approx. equal resistances RN = RP approx. equal rise tpLH and fall tpHL delays Analyze as an RC network 2W W Delay (D): tpHL = (ln 2) RNCL tpLH = (ln 2) RPCL Load for the next stage: EE141

Inverter with Load RW CL RW tp = k RWCL k is a constant, equal to 0.69 Delay RW CL RW Load (CL) tp = k RWCL k is a constant, equal to 0.69 Assumptions: no load -> zero delay Wunit = 1 EE141

Inverter with Load CP = 2Cunit 2W W Cint CL CN = Cunit Delay 2W W Cint CL Load CN = Cunit Delay = kRW(Cint + CL) = kRWCint + kRWCL = kRW Cint(1+ CL /Cint) = Delay (Internal) + Delay (Load) EE141

Delay Formula Cint = gCgin with g  1 f = CL/Cgin - effective fanout R = Runit/W ; Cint =WCunit tp0 = 0.69RunitCunit EE141

Apply to Inverter Chain Out CL 1 2 N tp = tp1 + tp2 + …+ tpN EE141

Optimal Tapering for Given N Delay equation has N - 1 unknowns, Cgin,2 – Cgin,N Minimize the delay, find N - 1 partial derivatives Result: Cgin,j+1/Cgin,j = Cgin,j/Cgin,j-1 Size of each stage is the geometric mean of two neighbors each stage has the same effective fanout (Cout/Cin) each stage has the same delay EE141

Optimum Delay and Number of Stages When each stage is sized by f and has same eff. fanout f: Effective fanout of each stage: Minimum path delay EE141

Example In Out CL= 8 C1 1 f f2 C1 CL/C1 has to be evenly distributed across N = 3 stages: EE141

Optimum Number of Stages For a given load, CL and given input capacitance Cin Find optimal sizing f For g = 0, f = e, N = lnF EE141

Optimum Effective Fanout f Optimum f for given process defined by g fopt = 3.6 for g=1 EE141

Buffer Design N f tp 1 64 65 2 8 18 3 4 15 4 2.8 15.3 1 64 1 8 64 1 4 16 64 1 64 22.6 2.8 8 EE141