GlueX electronics Collaboration Meeting December, 2003 Paul Smith

12,500 ADC channels 8,200 TDC channels Level 1 Trigger: 200 KHz X 5 KB/event = 1GB/sec Digital Pipeline Deadtimeless

Electronics Review Andy Lankford (UC Irvine) and Glenn Young (ORNL) at the GlueX Electronics Review - July

Generic Front End Preamp parameters chosen for improved S/N, signal rates, power dissipation, etc. On-detector digitization decreases cabling requirements but increases complexity and imposes more stringent requirements on reliability. Copper links should be used in high radiation areas. Pole-Zero CR-(RC) n Semi-Gaussian Shaper BLR isis CdCd CfCf RfRf Driver Discriminator LE, CFD, ZC ADCPipeline CopperFiber To DAQ Digitization Preamp

Single channel FADC prototype Test bed for: SPT converter chip Xilinx chip and software Mentor PCB & FPGA software Intellectual Property (PCI core) Robotic assembly

Next (final?) version 6U FADC Clock/ Sync Xilinx V2PRO PICMG 2.16 Small Xilinx Energy sum Ethernet

Cockcroft-Walton PMT base

Robotic Selective Assembly

F1 TDC Block Diagram

JLab TDC Module – Top & Bottom Sides

“Electronics” View of Trigger/DAQ Digital Pipeline Front End “Digitizer” FE/DAQ Interface Trigger Analog Data To ROC Event Block Buffers Every events Every event

Level 1 includes: Forward calorimeter energy sum Barrel calorimeter energy sum Track counts: –Vertex –Barrel –Forward

Photon Rates Level 1 Level 3 Physics Signal Software-based Level 3 System 10 7  /s Open and unbiased trigger Design for 10 8  /s 15 KHz events to tape Level 1 trigger system With pipeline electronics

Selected Review Conclusions: The decision to standardize all detector readout on a single TDC module design and a single Flash ADC module design is good, and will help simplify the overall electronics system design in a constructive way and conserve valuable engineering resources. More manpower will be needed in order to fully realize the GlueX electronics system. Considerable special (technical) expertise will also be required. The requirements and specifications of the analog front- end electronics are not yet adequately defined. This is coupled to the tentative status of some detector designs. The lack of full definition of detector designs may soon limit progress on electronics design,

Integration Electronics racks near detector (~100) Short cables, no extra delay Fiber optic connections from detector to counting house Access to detector components without uncabling

Integration Solenoid Tracking Cerenkov TOF FCAL