ARM (Advanced RISC Machine; initially Acorn RISC Machine) Load/store architecture 65 instructions (all fixed length – one word each = 32 bits) 16 registers Comparison and contrast of ARM, SPARC, and Intel x86 Similarities: 8-bit bytes (allows representation of ASCII-encoded character) Byte-addressable memory (address down to individual character) ARM, SPARC, x86

Similarities: 8-bit bytes (allows representation of ASCII-encoded character) Byte-addressable memory (address down to individual character) two's complement for signed integers floating point follows IEEE standard arithmetic, logical, and shift operations branching and calling instructions condition codes used for branch decisions stack frame support (sp, fp/bp) for procedure calls can be pipelined and have superscalar, multithreaded, and multicore implementations

ARM, SPARC, x86 Differences (cont’d): ARMSPARCX86 (8086) introduced in 1985 (ARM1) introduced in 1986 (version 7) introduced in 1978 (80386) 32-bit words 16-bit words 16 registers (actually 37 registers - additional registers have similar names for other modes) 32 general purpose registers (more on chip, but only 32 are visible at any one time 8 registers, most with special purpose (i.e., have fixed usage in certain operations fixed-length insts. (4 bytes) fixed-length insts. (4 bytes) variable-length insts. (1 – 6 bytes) load-store architecture reg-to-reg ops load-store architecture reg-to-reg ops extended accumulator architecture, reg-to-mem and mem-to-reg ops

ARM, SPARC, x86 Differences (cont’d): ARMSPARCX86 (8086) normal branchesdelayed branchesnormal branches RISC - reduced instruction set computer => streamlined for ease of hardware implementation RISCCISC - complex inst. set computer => complicated operations (some of this is due to legacy, i.e., need for compatibility with previous 8080 and 8085 microprocessors) bi-endianbig endianlittle endian floating point uses a separate set of 32 registers floating point uses a separate stack requires aligned operandsRequires aligned operands unaligned operand access in hardware