1. THE sic mACHINE
CSCI/CMPE 3334
David Egle

2. The SIC machine Simplified Instruction Computer
Hypothetical machine which includes hardware features most often found (well, in 1997)
Two versions
standard model
XE model
extra equipment / extra expensive
upward compatible

3. SIC Machine Architecture (1/4)
Memory
byte: 8 bits
word: 3 bytes
size: 2^15 = 32K bytes
address: byte or lowest numbered byte in a word
Data formats
integer: word, 2’s complement
character: byte, ASCII representation

4. SIC Machine Architecture (2/4)
Registers
5 registers – each one word in length
Name
Number
Use A
Accumulator X 1
Index register L 2
Linkage register PC 8
Program counter SW 9
Status word

5. SIC Machine Architecture (3/4)
Instruction format
three fields
opcode: 8 bits
index bit: 1 bit
address: 15 bits
Addressing modes
Direct: x = 0, Target Address TA = address
Indexed: x = 1, TA = address + (X)
Instruction set
25 instructions – see appendix
opcode x
address

6. SIC Machine Architecture (4/4)
Input and Output
to/from rightmost byte of register A
one byte at a time
each device is assigned 8-bit code
Instructions
TD – test device
RD – read data
WD – write data

7. SIC/XE Machine Architecture (1/7)
Based on SIC, but with additions as noted below
Memory
Size: 2^20 = 1Mbyte
Additional data format
floating point: 6 bytes (2 words)
high-order bit of the fraction must be 1
exponent is unsigned binary number
value = f x 2^(exp – 1024)
zero represented by all bits set to zero

8. SIC/XE Machine Architecture (2/7)
Extra registers
Name
Number
Use B 3
Base register S 4
General T 5 F 6
Floating point accumulator; 6 bytes

9. SIC/XE Machine Architecture (3/7)
Instruction formats
4 formats: 1, 2, 3, and 4 bytes 8
opcode 8 4
opcode r1 r2 6 1 12 op n i x b p e
displacement (disp) 6 1 20 op n i x b p e
address

10. SIC/XE Machine Architecture (4/7)
Additional instructions
load and store new registers
handle floating point
register – register operations
I/O channels perform I/O while CPU is executing other instructions

11. SIC/XE Machine Architecture (5/7)
Addressing modes (formats 3 and 4)
Relative addressing (e = 0)
b = 1, p = 0  TA = (B) + disp; disp is unsigned integer
b = 0, p = 1  TA = (PC) + disp; disp is 2’s complement
b = 0, p = 0  TA = disp (12 bit address)
Direct addressing (e = 1)
b = 0, p = 0  TA = disp (20 bit address)
Indexed addressing (x = 1)
add (X) to calculated value of TA

12. SIC/XE Machine Architecture (6/7)
Addressing modes cont’d (formats 3 and 4)
immediate addressing
i = 1, n = 0  TA is the operand
indirect addressing
i = 0, n = 1  (TA) is the address of the operand
simple addressing
i = 1, n = 1  use one of the modes on the previous slide
compatibility mode
i = 0, n = 0  use SIC format

13. SIC/XE Machine Architecture (7/7)
Compatibility mode
Note that all SIC instructions end with 00
All SIC instructions are 3 bytes (format 3)
bits b, p, and e, are considered part of address

14. Examples of SIC and SIC/XE code
Read section of the text
Note that I will not require that you write SIC code, but you should understand what the code does.