1. Chapter Six Sun SPARC Architecture

2. SPARC Processor The name SPARC stands for Scalable Processor Architecture SPARC architecture follows the RISC design philosophy by stressing importance of – Large CPU register file – Similar register window features

3. RISC Vs CISC The historical background: – In first 25 years (1945-70) performance came from both technology and design. – Design considerations: o small and slow memories: compact programs are fast. o small no. of registers: memory operands are used instead o attempts to bridge the semantic gap: model high level language features in instructions. o no need for portability: same vendor application, OS and hardware. o backward compatibility: every new ISA must carry the good and bad of all past ones. Result: powerful and complex instructions that are rarely used. Such type of processors were classified as CISC.

4. CISC CISC is an acronym for Complex Instruction Set Computer. These chips are easy to program and make efficient use of memory. CISC philosophy made sense as the earliest machines were programmed in assembly language and memory was slow and expensive Most common microprocessor designs such as Intel 80x86 and Motorola 68K series followed the CISC philosophy.

5. RISC Vs CISC Later it was found as follows:

6. What is RISC? Reduced Instruction Set Computer(RISC) is a type of microprocessor architecture that utilizes a small, highly-optimized set of instructions than a more specialized set of instructions often found in other types of architectures The characteristic of most RISC processors are: – one cycle execution time: RISC processors have a CPI (clock per instruction) of one cycle. This is for the optimization of CPU pipelining – large number of registers: RISC design generally incorporates a larger number of registers to reduce the number of interactions with memory

7. RISC Reduced instruction set. Less complex, simple instructions. Hardwired control unit and machine instructions. Few addressing schemes for memory operands with two basic instructions - LOAD and STORE Many symmetric registers which are organised into a register file. CISC Extensive instructions. Complex and efficient machine instructions. Microencoding of the machine instructions. Extensive addressing capabilities for memory operations. Relatively few registers.

8. SPARC Processor SPARC Processor was introduced by Sun Microsystems in 1987 as an architectural family. It is an open architecture : semiconductor vendors can produce SPARC chips using various implementation domains: CMOS,ECL and GaAs

9. SPARC Features A linear 32-bit address space Few and simple instruction formats — All instructions are 32 bits wide. – Only 3 basic instruction formats – Uniform placement of opcode and register address fields in instruction – Only LOAD and STORE instructions access memory and I/O. Few addressing modes — An address may be “register + register” or “register+immediate.”

10. SPARC Features Triadic register addresses— Most instructions operate on two register operands (or one register and a constant) and place the result in a third register. A large “windowed” register file — At any one instant, a program sees 8 global integer registers plus a 24-register window into a larger register file. A separate floating-point register file

11. SPARC Features Delayed control transfer— The processor always fetches the next instruction after a delayed control-transfer instruction. Fast trap handler Tagged instructions Multiprocessor synchronization instructions Coprocessor— The architecture defines a straightforward coprocessor instruction set, in addition to the floating-point instruction set.

12. SPARC Architecture SPARC is an instruction set architecture (ISA) with 32-bit integer and 32-, 64-,and 128-bit floating point as its principal data types. SPARC processor logically comprises 3 units: – an Integer Unit (IU) – a Floating-Point Unit (FPU) – an optional Coprocessor (CP), each with its own registers. (32-bits wide).

13. SPARC Processor SPARC processor can be in either of 2 modes: – Supervisor mode: The processor can execute any instruction including the privileged instructions. – User mode: “User Application” programs will be executed in user mode. An attempt to execute a privileged instruction will cause a trap to supervisor software.

14. THE MODULES Integer Unit (IU) Floating-Point Unit (FPU) CoProcessor (CP)

15. THE MODULES Integer Unit (IU) Floating-Point Unit (FPU) CoProcessor (CP)

16. INTEGER UNIT (IU) Contains the general purpose registers and controls the overall operation of the processor. Executes the integer arithmetic instructions and computes memory addresses for loads and stores. Maintains the program counters and controls instruction execution for the FPU and the CP. May contain from 40 to 520 general-purpose 32-bit registers It corresponds to – 8 global registers and – a circular stack of from 2 to 32 sets of 16 registers known as register windows. – Thus (2*16=32+8=40) to (32*16+8 =520) Integer Unit (IU)

17. REGISTER WINDOW CONCEPT Each instruction can access the 8-globals and a register window A 24- register window comprises – 8 in – 8 local registers – 8 out registers( which are together with the 8 in registers of an adjacent register set, addressable from the current window) Integer Unit (IU)

18. THE MODULES Integer Unit (IU) Floating-Point Unit (FPU) CoProcessor (CP)

19. FLOATING-POINT UNIT (FPU) The FPU has thirty-two 32-bit-wide registers. – Double-precision values occupy an even-odd pair of registers – Quad-precision values occupy a quad aligned group of four registers. Floating point load/store instructions are used to move data between the FPU and memory. The memory address is calculated by IU FPop(Floating Point Operate) instructions perform the actual Floating Point Arithmetic

20. THE MODULES Integer Unit (IU) Floating-Point Unit (FPU) CoProcessor (CP)

21. Coprocessor Unit The instruction set includes support for a single, implementation-dependent coprocessor. The coprocessor has its own set of 32-bit registers. Coprocessor load/store instructions are used to move data between the coprocessor registers and memory.

22. Data Formats

23. SPARC Data Formats The SPARC architecture recognizes three fundamental data formats (or types): – Signed Integer— 8, 16, 32, and 64 bits – Unsigned Integer— 8, 16, 32, and 64 bits – Floating-Point — 32, 64, and 128 bits The format widths are defined as – Byte — 8 bits – Halfword— 16 bits – Word/Singleword — 32 bits

24. SPARC Data Formats – Tagged Word— 32 bits (30-bit value plus 2 tag bits) – Doubleword— 64 bits – Quadword— 128 bits

25. Signed Integer Signed Integer formats encode two’s- complement whole numbers

26. Signed Integer

27. Unsigned Integer Unsigned Integer formats are general-purpose and hence they do not encode any particular data type. They can represent a whole number, string, fraction, boolean value, etc.

28. Unsigned Integer

30. Floating Point Numbers