Lecture #20 Page 1 ECE 4110– Digital Logic Design Lecture #21 Agenda 1.MSI: Carry Look-Ahead Adders Announcements 1.N/A.

Lecture #20 Page 2 Carry Look Ahead Adders Addition – Carry Look Ahead Adder - We've seen a Ripple Carry Adder topology (RCA) - this is good for simplicity and design-reuse - however, the delay increases linearly with the number of bits t RCA = n·t Full-Adder - different topologies within the full-adder to reduce delay (Δt) will have a n·Δt effect - the linear increase in delay comes from waiting for the Carry to Ripple through

Lecture #20 Page 3 Carry Look Ahead Adders Addition – Carry Look Ahead Adder - to avoid the ripple, we can build a Carry Look-Ahead Adder (CLA) - this circuit calculates the carry for all Full-Adders at the same time - we define the following intermediate stages of a CLA: Generate"g", an adder (i) generates a carry out (C i+1 )under input conditions A i and B i independent of A i-1, B i-1, or Carry In (C i ) A i B i C i we can say that:g i = A i ·B i remember, g does NOT consider carry in (C i )

Lecture #20 Page 4 Carry Look Ahead Adders Addition – Carry Look Ahead Adder Propagate"p", an adder (i) will propagate (or pass through) a carry in (C i ) depending on input conditions A i and B i, : C i A i B i C i p i is defined when there is a carry in, so we ignore the row entries where C i = if we only look at the C i =1 rows we can say that: p i = (A i +B i )·C i

Lecture #20 Page 5 Carry Look Ahead Adders Addition – Carry Look Ahead Adder - said another way, Adder(i) will "Generate" a Carry Out (C i+1 ) if: g i = A i ·B i and it will "Propagate" a Carry In (C i ) when p i = (A i +B i )·C i - a full expression for the Carry Out (C i+1 ) in terms of p and g is given by: C i+1 = g i +p i ·C i - this is good, but we still generate Carry's dependant on previous stages (i-1) of the iterative circuit

Lecture #20 Page 6 Carry Look Ahead Adders Addition – Carry Look Ahead Adder - We can eliminate this dependence by recursively expanding each Carry Equation ex) 4 bit Carry Look Ahead Logic C 1 = g 0 +p 0 ·C 0 (2-Level Product-of-Sums) C 2 = g 1 +p 1 ·C 1 C 2 = g 1 +p 1 ·(g 0 +p 0 ·C 0 ) C 2 = g 1 +p 1 ·g 0 +p 1 ·p 0 ·C 0 (2-Level Product-of-Sums) C 3 = g 2 +p 2 ·C 2 C 3 = g 2 +p 2 ·(g 1 +p 1 ·g 0 +p 1 ·p 0 ·C 0 ) C 3 = g 2 +p 2 ·g 1 +p 2 ·p 1 ·g 0 +p 2 ·p 1 ·p 0 ·C 0 (2-Level Product-of-Sums) C 4 = g 3 +p 3 ·C 3 C 4 = g 3 +p 3 ·(g 2 +p 2 ·g 1 +p 2 ·p 1 ·g 0 +p 2 ·p 1 ·p 0 ·C 0 ) C 4 = g 3 +p 3 ·g 2 +p 3 ·p 2 ·g 1 +p 3 ·p 2 ·p 1 ·g 0 +p 3 ·p 2 ·p 1 ·p 0 ·C 0 (2-Level Product-of-Sums) - this gives us logic expressions that can generate a next stage carry based upon ONLY the inputs to the adder and the original carry in (C 0 )

Lecture #20 Page 7 Carry Look Ahead Adders Addition – Carry Look Ahead Adder - the Carry Look Ahead logic has 3 levels 1) g and p logic 2) product terms in the C i equations 3) sum terms in the C i equations - the Sum bits require 2 levels of Logic 1) A i  B i  C i NOTE:A Full Adder made up of 2 Half Adders has 3 levels. But the 3rd level is used in the creation of the Carry Out bit. Since we do not use it in a CLA, we can ignore that level. - So a CLA will have a total of 5 levels of Logic

Lecture #20 Page 8 Carry Look Ahead Adders Addition – Carry Look Ahead Adder - the 5 levels of logic are fixed no matter how many bits the adder is (really?) - In reality, the most significant Carry equation will have i+1 inputs into its largest sum/product term - this means that Fan-In becomes a problem since real gates tend to not have more than 4-6 inputs - When the number of inputs gets larger than the Fan-In, the logic needs to be broken into another level ex) A+B+C+D+E = (A+B+C+D)+E - In the worst case, the logic Fan-In would be 2. Even in this case, the delay associated with the Carry Look Ahead logic would be proportional to log 2 (n) - Area and Power are also concerns with CLA's. Typically CLA's are used in computationally intense applications where performance outweighs Power and Area.

Lecture #20 Page 9 Carry Look Ahead Adders Adders in VHDL - (+) and (-) are not defined for STD_LOGIC_VECTOR - The Package STD_LOGIC_ARITH gives two data types: UNSIGNED (3 downto 0) := "1111"; SIGNED (3 downto 0) := "1111"; these are still resolved types (STD_LOGIC), but the equality and arithmetic operations are slightly different depending on whether you are using Signed vs. Unsigned Considerations - when adding signed and unsigned numbers, the type of the result will dictate how the operands are handled/converted - if assigning to an n-bit, SIGNED result, an n-1 UNSIGNED operand will automatically be converted to signed by extending its vector length by 1 and filling it with a sign bit (0)

Lecture #20 Page 10 Carry Look Ahead Adders Adders in VHDL ex)A,B: inUNSIGNED (7 downto 0); C: inSIGNED (7 downto 0); D: inSTD_LOGIC_VECTOR (7 downto 0); S: outUNSIGNED (8 downto 0); T: outSIGNED (8 downto 0); U: outSIGNED (7 downto 0); S(7 downto 0) <= A + B;-- 8-bit UNSIGNED addition, not considering Carry S <= ('0' & A) + ('0' & B);-- manually increasing size of A and B to include Carry. Carry will be kept in S(9) T <= A + C;-- T is SIGNED, so A's UNSIGNED vector size is increased by 1 and filled with '0' as a sign bit U <= C + SIGNED(D);-- D is converted (considered) to SIGNED, not increased in size U <= C + UNSIGNED(D);-- D is converted (considered) to UNSIGNED, not increased in size