Dec 1, 2003 Slide 1 Copyright, © Zenasis Technologies, Inc. Flex-Cell Optimization A Paradigm Shift in High-Performance Cell-Based Design A Paradigm Shift in High-Performance Cell-Based Design

Dec 1, 2003 Slide 2 Copyright, © Zenasis Technologies, Inc. The Power-User Dilemma Custom Team=400 3 GHz, 3 Years Flex-Cell Opt Team= MHz 6 Months FPGA ASIC/COT Team= MHz 9 Months Cost / TTM Speed, Power, Area Takes too long! Results aren’t good enough!

Dec 1, 2003 Slide 3 Copyright, © Zenasis Technologies, Inc. The Timing Dilemma Design Team clock target – 350 MHz On Post-logic synth./Post-placement STA –Only 300 MHz – Problem!! Options –Design change Rewrite RTL – Tapeout Delay!! –Better technology Smaller geometry – Tapeout delay and NRE cost!! Low-k technology – Yield hit!! –Better tools Flex-Cell Optimization –Custom-design benefits in std cell flow Design Team clock target – 350 MHz On Post-logic synth./Post-placement STA –Only 300 MHz – Problem!! Options –Design change Rewrite RTL – Tapeout Delay!! –Better technology Smaller geometry – Tapeout delay and NRE cost!! Low-k technology – Yield hit!! –Better tools Flex-Cell Optimization –Custom-design benefits in std cell flow

Dec 1, 2003 Slide 4 Copyright, © Zenasis Technologies, Inc. Root of the Problem Various past studies, including a special session at DAC 2000 Std-Cell based design “an order of magnitude” lower performance than custom, at same process node –Architecture –Fixed cell library –Layout Std-Cell based design “an order of magnitude” lower performance than custom, at same process node –Architecture –Fixed cell library –Layout Fixed cell library can account for as much as 25% of the performance shortfall

Dec 1, 2003 Slide 5 Copyright, © Zenasis Technologies, Inc. Rich vs Smart Simply creating a “richer” cell library does not solve problem –Too many cells hinder automated optimization –Missing design-specific context information –Well-known matching problems for larger cells Simply creating a “richer” cell library does not solve problem –Too many cells hinder automated optimization –Missing design-specific context information –Well-known matching problems for larger cells Custom-crafted cells, for specific design, can inject large timing gains late in the design cycle Compute-intensive process –Transistor netlist optimization –Cell layout creation –View generation Custom-crafted cells, for specific design, can inject large timing gains late in the design cycle Compute-intensive process –Transistor netlist optimization –Cell layout creation –View generation

Dec 1, 2003 Slide 6 Copyright, © Zenasis Technologies, Inc. Flex-Cell Optimization -- Concept Transistor Level Physical Level Physical Level Logical Level Physical Level Logical Level Flex-Cell Opt Optimization at Gate, Transistor & Physical Levels

Dec 1, 2003 Slide 7 Copyright, © Zenasis Technologies, Inc. Prior Work Manual custom-crafting of cells, is well established –Tactical cells: every high-performance design project uses some Manual custom-crafting of cells, is well established –Tactical cells: every high-performance design project uses some Automated transistor-level netlist creation/optimization –Fishburn, Dunlop(1985): TILOS, transistor sizing –Gavrilov et al (1997): Library-less synthesis –Kanecko, Tian (1998): Concurrent cell generation and mapping of digital logic –Liu, Abraham (1999): Transistor-level synthesis of combinational logic Automated transistor-level netlist creation/optimization –Fishburn, Dunlop(1985): TILOS, transistor sizing –Gavrilov et al (1997): Library-less synthesis –Kanecko, Tian (1998): Concurrent cell generation and mapping of digital logic –Liu, Abraham (1999): Transistor-level synthesis of combinational logic

Dec 1, 2003 Slide 8 Copyright, © Zenasis Technologies, Inc. Flex-Cell Optimization Targets Eliminate deficiency due to fixed cell library –Boost performance by 15% - 25% Close aggressive timing in days Retain proven existing cell-based design flow Use high-yield process, still get performance Minimal increase in die-size or power Get custom-design performance from std-cell- based flow Eliminate deficiency due to fixed cell library –Boost performance by 15% - 25% Close aggressive timing in days Retain proven existing cell-based design flow Use high-yield process, still get performance Minimal increase in die-size or power Get custom-design performance from std-cell- based flow

Dec 1, 2003 Slide 9 Copyright, © Zenasis Technologies, Inc. STA Cluster formation Critical Paths Key Steps Flex-cell (custom crafted) creation Gate-level optimization 1 Cell 13 Transistors 6 Wires a b d a c b a d c a 4 Cells 22 Transistors 9 Wires a c d b a Post synthesis netlist d

Dec 1, 2003 Slide 10 Copyright, © Zenasis Technologies, Inc. Flex-Cell Optimization with Physicals Physically-aware STA –Placement aware Congestion Blockage –Multiple levels of accuracy for route info Steiner estimates Global route Detailed route** Physically-aware STA –Placement aware Congestion Blockage –Multiple levels of accuracy for route info Steiner estimates Global route Detailed route** Physically-driven optimization –Physically-aware clustering and mapping –Physically-aware gate-level optimizations –Low disturbance to existing placement –Incremental legalization of placement –Incremental re-computation of routes/estimates Physically-driven optimization –Physically-aware clustering and mapping –Physically-aware gate-level optimizations –Low disturbance to existing placement –Incremental legalization of placement –Incremental re-computation of routes/estimates

Dec 1, 2003 Slide 11 Copyright, © Zenasis Technologies, Inc. Sample Flex-Cell Tx-Level View of Gate Cluster 22 Transistors Path depth = 3 levels b b d d c c a c a a y c 13 Transistors; Path depth = 2 levels Critical Path: a -> y Rise = 0.12 ns; Fall = 0.10 ns a b d a c b a d d c a y After Tx-Level Optimization Before After Rise (critical) 0.26ns 0.12ns Fall (critical) 0.31ns 0.10ns # Cells 4 1 # Transistors Path depth 3 2 # nets 9 7 Tx Opt Custom-Crafted Flex-Cell 1 Cell, 7 nets Critical Path: a -> y Rise = 0.12 ns ; Fall = 0.10 ns Gate-Level Cluster a c d b y Critical Path: a -> y Rise = 0.26 ns ; Fall = 0.31 ns 4 Cells, 9 nets a

Dec 1, 2003 Slide 12 Copyright, © Zenasis Technologies, Inc. Transistor-Level Optimization

Dec 1, 2003 Slide 13 Copyright, © Zenasis Technologies, Inc. Key Issues Judicious mix of gate-level and transistor-level optimization Judicious mix of discrete and continuous transistor sizing Effective use of transistor-level restructuring Fast and accurate transistor-level simulation –50x to 100x faster than Spice Accurate estimation of parasitics given transistor- level netlist Judicious mix of gate-level and transistor-level optimization Judicious mix of discrete and continuous transistor sizing Effective use of transistor-level restructuring Fast and accurate transistor-level simulation –50x to 100x faster than Spice Accurate estimation of parasitics given transistor- level netlist

Dec 1, 2003 Slide 14 Copyright, © Zenasis Technologies, Inc. Impact On a Sample Critical Path Original Critical Path Optimized Path 0.20 Flex-Cell Flex-Cell % Improvement

Dec 1, 2003 Slide 15 Copyright, © Zenasis Technologies, Inc. Results (ZenTime  ) 38K+ instance design 16% performance boost –297 MHz --> 344 MHz Implemented in a 0.13u process Added 132 flex-cells, 5,927 instances Without increasing power or area 38K+ instance design 16% performance boost –297 MHz --> 344 MHz Implemented in a 0.13u process Added 132 flex-cells, 5,927 instances Without increasing power or area

Dec 1, 2003 Slide 16 Copyright, © Zenasis Technologies, Inc. Impact on Global Timing Initial frequency: 297 MHz Final frequency: 344 MHz Initial frequency: 297 MHz Final frequency: 344 MHz

Dec 1, 2003 Slide 17 Copyright, © Zenasis Technologies, Inc. Timing Optimization Results with physicals (def, sdf, …) with wire loads

Dec 1, 2003 Slide 18 Copyright, © Zenasis Technologies, Inc. I/O & Design Flow GDSII Back-end Design Extraction & Verification Detailed Route Front-end Design Constraints Design Library Flex-Cell Opt Timing Physical Synthesis Physical Gatelevel Opt. Discrete Sizing Cont. Sizing Clustering Timing Interface library.lib library.lef library.cdl netlist.v netlist.def constr.sdc tech.bsim3 netlist.set_load netlist.sdf opt_netlist.v opt_netlist.def flex-cell.est.lib flex-cell.est.lef flex-cell.cdl Flex-Cell Factory

Dec 1, 2003 Slide 19 Copyright, © Zenasis Technologies, Inc. Automated Flex-Cell Generation Tool Suite and Flow Sized spice netlists Cell Architecture gds lef ant. lef eqn.v mos.v lumpedC.sp distrRC.sp Layout Functional Spice TimingPower Noise/ glitch.lib.db.tlf Reports.lib ??

Dec 1, 2003 Slide 20 Copyright, © Zenasis Technologies, Inc. Summary New dimension in optimization of cell-based designs Essential to find the “right balance” between gate-level and transistor-level optimization Better design quality, higher runtime Timing, Area, Power no longer a simple trade- off –Possible to improve more than one, simultaneously Many challenges –Lots of research opportunities!! New dimension in optimization of cell-based designs Essential to find the “right balance” between gate-level and transistor-level optimization Better design quality, higher runtime Timing, Area, Power no longer a simple trade- off –Possible to improve more than one, simultaneously Many challenges –Lots of research opportunities!!

Dec 1, 2003 Slide 21 Copyright, © Zenasis Technologies, Inc. The History of Methodology Shifts Netlist schematic Netlist optimization Logic synthesis Physical synthesis Flex-cell optimization Flex-cell synthesis Physical optimization