Topics Basic fabrication steps. Transistor structures.

Slides:

Advertisements

Similar presentations

CMOS Fabrication EMT 251.

Advertisements

MODULE SYSTEM LOGIC GATE CIRCUIT DQ CMOS Inverter ASIC Full-Custom Semi-Custom Programmable FPGA PLD Cell-Based Gate Arrays General Purpose DRAM & SRAM.

Simplified Example of a LOCOS Fabrication Process

VLSI Design Lecture 2: Basic Fabrication Steps and Layout

CMOS Fabrication MOS Device Structure and Operation NMOS Circuits

Lecture 11: MOS Transistor

Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania ECE VLSI Circuit Design Lecture 3 - Transistors,

Modern VLSI Design 2e: Chapter 2 Copyright  1998 Prentice Hall PTR Topics n Basic fabrication steps n Transistor structures n Basic transistor behavior.

Elettronica D. AA Digital Integrated Circuits© Prentice Hall 1995 Manufacturing Process CMOS Manufacturing Process.

Chap. 5 Field-effect transistors (FET) Importance for LSI/VLSI –Low fabrication cost –Small size –Low power consumption Applications –Microprocessors –Memories.

Lecture #51 Lecture #5 – VLSI Design Review zPhotolithography zPatterning Silicon zProcess steps used are: yStarts with Si wafer yThermal oxidation yPhotoresist.

Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR Topics n Basic fabrication steps. n Transistor structures. n Basic transistor.

Device Fabrication Example

EE141 © Digital Integrated Circuits 2nd Manufacturing 1 Manufacturing Process I Dr. Shiyan Hu Office: EERC 518 Adapted and modified from Digital Integrated.

Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR Topics n Derivation of transistor characteristics.

ECE 342 Electronic Circuits 2. MOS Transistors

CS/EE 6710 CMOS Processing. N-type Transistor + - i electrons Vds +Vgs S G D.

２． Transistors and Layout Fabrication techniques Transistors and wires Design rule for layout Basic concepts and tools for Layout.

The Devices Digital Integrated Circuit Design Andrea Bonfanti DEIB

Jan M. Rabaey The Devices Digital Integrated Circuits© Prentice Hall 1995 Introduction.

VLSI Design Lecture 2: Basic Fabrication Steps and Layout Mohammad Arjomand CE Department Sharif Univ. of Tech. Adapted with modifications from Harris’s.

VLSI, Lecture 1 A review of microelectronics and an introduction to MOS technology Department of Computer Engineering, Prince of Songkla.

Modern VLSI Design 4e: Chapter 2 Copyright  2009 Prentice Hall PTR Topics n Basic fabrication steps. n Transistor structures. n Basic transistor behavior.

Modern VLSI Design 4e: Chapter 2 Copyright  2009 Prentice Hall PTR Topics n Derivation of transistor characteristics.

Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR Topics n Derivation of transistor characteristics.

CMOS Analog Design Using All-Region MOSFET Modeling 1 CMOS Analog Design Using All-region MOSFET Modeling Chapter 3 CMOS technology, components, and layout.

Chapter 4 Field-Effect Transistors

FPGA-Based System Design: Chapter 2 Copyright  2003 Prentice Hall PTR Topics n Off-chip connections.

Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR Topics n Design rules and fabrication. n SCMOS scalable design rules. n Stick.

FPGA-Based System Design: Chapter 2 Copyright  2004 Prentice Hall PTR IC Fabrication n Basic fabrication steps. n Transistor structures. n VLSI Characteristics.

Modern VLSI Design 3e: Chapter 2 Partly from 2002 Prentice Hall PTR week2-1 Lecture 4 Transistor as Switch Jan

Semiconductor Manufacturing Technology Michael Quirk & Julian Serda © October 2001 by Prentice Hall Chapter 9 IC Fabrication Process Overview.

Microelectronic Circuit Design McGraw-Hill Chapter 4 Field-Effect Transistors Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock.

EE141 © Digital Integrated Circuits 2nd Manufacturing 1 Manufacturing Process Dr. Shiyan Hu Office: EERC 731 Adapted and modified from Digital Integrated.

Lecture 24a, Slide 1EECS40, Fall 2004Prof. White Lecture #24a OUTLINE Device isolation methods Electrical contacts to Si Mask layout conventions Process.

Fabrication Technology(1)

ECE442: Digital ElectronicsCSUN, Spring-2010-Zahid MOS Transistor ECE442: Digital Electronics.

1 Chapter 5. Metal Oxide Silicon Field-Effect Transistors (MOSFETs)

UNIT I MOS TRANSISTOR THEORY AND PROCESS TECHNOLOGY

Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR Topics n Wire and via structures. n Wire parasitics. n Transistor parasitics.

EE141 © Digital Integrated Circuits 2nd Devices 1 Goal of this lecture  Present understanding of device operation  nMOS/pMOS as switches  How to design.

CMOS Fabrication nMOS pMOS.

VLSI Design Lecture 3: Parasitics of CMOS Wires Mohammad Arjomand CE Department Sharif Univ. of Tech. Adapted with modifications from Harris’s lecture.

NMOS FABRICATION 1. Processing is carried out on a thin wafer cut from a single crystal of silicon of high purity into which the required p-impurities.

Modern VLSI Design 3e: Chapter 7 Copyright  1998, 2002 Prentice Hall PTR Topics n Power/ground routing. n Clock routing. n Floorplanning tips. n Off-chip.

CORPORATE INSTITUTE OF SCIENCE & TECHNOLOGY, BHOPAL DEPARTMENT OF ELECTRONICS & COMMUNICATIONS NMOS FABRICATION PROCESS - PROF. RAKESH K. JHA.

Modern VLSI Design 2e: Chapter 2 Copyright  1998 Prentice Hall PTR Topics n Basic fabrication steps n Transistor structures n Basic transistor behavior.

1 Overview of Fabrication Processes of MOSFETs and Layout Design Rules.

Dynamic Behavior of MOS Transistor. The Gate Capacitance t ox n + n + Cross section L Gate oxide x d x d L d Polysilicon gate Top view Gate-bulk overlap.

Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week3-1 Lectures 6, 7 and 8 Transistor Function Jan. 17, 20 and 22, 2003.

Silicon Design Page 1 The Creation of a New Computer Chip.

CMOS FABRICATION.

Full-Custom Design ….TYWu

Microelectronic Circuit Design McGraw-Hill Chapter 4 Field-Effect Transistors Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock.

EE314 IBM/Motorola Power PC620 IBM Power PC 601 Motorola MC68020 Field Effect Transistors.

UNIT II : BASIC ELECTRICAL PROPERTIES

MOS Capacitance Unit IV : GATE LEVEL DESIGN VLSI DESIGN 17/02/2009

Chapter 3 Fabrication, Layout, and Simulation.

Topics Design rules and fabrication SCMOS scalable design rules

Manufacturing Process I

Prof. Haung, Jung-Tang NTUTL

Topics Basic fabrication steps. Transistor structures.

VLSI Design MOSFET Scaling and CMOS Latch Up

Introduction to Layout Inverter Layout Example Layout Design Rules

Manufacturing Process I

Manufacturing Process I

Copyright © 2004 The McGraw-Hill Companies, Inc. All rights reserved.

Presentation transcript:

Topics Basic fabrication steps. Transistor structures. Basic transistor behavior. Latch up.

Fabrication processes IC built on silicon substrate: some structures diffused into substrate; other structures built on top of substrate. Substrate regions are doped with n-type and p-type impurities. (n+ = heavily doped) Wires made of polycrystalline silicon (poly), multiple layers of aluminum/copper (metal). Silicon dioxide (SiO2) is insulator.

Simple cross section SiO2 metal3 metal2 metal1 transistor via poly n+ substrate n+ p+ substrate

Photolithography Mask patterns are put on wafer using photo-sensitive material:

Process steps First place tubs to provide properly-doped substrate for n-type, p-type transistors: p-tub n-tub substrate

Process steps, cont’d. Pattern polysilicon before diffusion regions: gate oxide poly poly p-tub n-tub

Process steps, cont’d Add diffusions, performing self-masking: poly p-tub n+ n+ n-tub p+ p+

Process steps, cont’d Start adding metal layers: metal 1 metal 1 vias poly poly p-tub n+ n+ n-tub p+ p+

Level 2 metal Polish SiO2 before adding metal 2: metal 2 metal 1 vias poly poly p-tub n+ n+ p-tub p+ p+

Transistor structure n-type transistor:

Transistor layout n-type (tubs may vary): L w

Drain current characteristics

Drain current Linear region (Vds < Vgs - Vt): Id = k’ (W/L)(Vgs - Vt)(Vds - 0.5 Vds2) Saturation region (Vds >= Vgs - Vt): Id = 0.5k’ (W/L)(Vgs - Vt) 2

90 nm transconductances Typical parameters: n-type: p-type: kn’ = 13 A/V2 Vtn = 0.14 V p-type: kp’ = 7 A/V2 Vtp = -0.21 V

Current through a transistor Use 90 nm parameters. Let W/L = 3/2. Measure at boundary between linear and saturation regions. Vgs = 0.25V: Id = 0.5k’(W/L)(Vgs-Vt)2= 0.12 A Vgs = 1V: Id = 7.2 mA

Basic transistor parasitics Gate to substrate, also gate to source/drain. Source/drain capacitance, resistance.

Basic transistor parasitics, cont’d Gate capacitance Cg. Determined by active area. Source/drain overlap capacitances Cgs, Cgd. Determined by source/gate and drain/gate overlaps. Independent of transistor L. Cgs = Col W Gate/bulk overlap capacitance.

Latch-up CMOS ICs have parastic silicon-controlled rectifiers (SCRs). When powered up, SCRs can turn on, creating low-resistance path from power to ground. Current can destroy chip. Early CMOS problem. Can be solved with proper circuit/layout structures.

Parasitic SCR circuit I-V behavior

Parasitic SCR structure

Solution to latch-up Use tub ties to connect tub to power rail. Use enough to create low-voltage connection.