1 COMP541 Interrupts, DMA, Serial I/O Montek Singh April 18, 2012

2Interrupts  Two main kinds  Internal Error when executing an instruction Error when executing an instruction  Floating point exception  Virtual memory page fault  Trying to access protected memory  Invalid opcode! System call requested by software System call requested by software  To request OS services  External I/O I/O

3Internal  More complicated because two possible actions may abort instruction may abort instruction  access to protected memory not allowed or, OS corrects the situation and restarts instruction or, OS corrects the situation and restarts instruction  e.g., virtual memory page fault  Question: What happens for arithmetic overflow/divide-by-0? What happens for arithmetic overflow/divide-by-0?

4 When Interrupt Occurs  Interrupt enable register Sometimes levels of interrupts individually enabled/disabled Sometimes levels of interrupts individually enabled/disabled  PC is changed to new location One or more interrupt locations stored One or more interrupt locations stored  “vectored interrupts” Or a fixed location Or a fixed location  example: MIPS (e.g., 0xC )  Old PC saved to register or stack Many machines have stack pointer Many machines have stack pointer

5Registers  Sometimes registers saved by hardware Some machines have one or more sets of registers Some machines have one or more sets of registers  Often: software must save registers Push them onto stack Push them onto stack  Return from interrupt Some CPUs provide a special instruction to return from interrupt Some CPUs provide a special instruction to return from interrupt  “rfi” or “iret” Others use the standard procedure return instruction Others use the standard procedure return instruction  jr, ret, etc. Restore registers before returning Restore registers before returning

6 Cause of Interrupt  Need way to determine what caused interrupt Note it can be more than one thing Note it can be more than one thing  Vectored Interrupts Different types cause branches to different locations Different types cause branches to different locations Sometimes prioritized Sometimes prioritized  Register to store cause “Cause” register “Cause” register

7 Supervisory Mode  Modern computers have user mode and one or more “supervisory modes”  User mode restricted Can’t write to many system registers, such as interrupt enable Can’t write to many system registers, such as interrupt enable Can’t write to some parts of memory Can’t write to some parts of memory Usually I/O restricted Usually I/O restricted  Interrupts cause switch to supervisory mode In this mode, software has access to several privileged parts of the system In this mode, software has access to several privileged parts of the system  e.g.: kernel memory, IE register, etc. Question: Which interrupts? Question: Which interrupts?

Some Interrupt Hardware  An example implementation Interrupts ORed Interrupts ORed Response if IE and at end of instruction Response if IE and at end of instruction Ack interrupt Ack interrupt Vector address to PC Vector address to PC Save PC on stack Save PC on stack 8

9 Potential Microcode The following is a typical sequence of actions taken by the CPU upon triggering of an interrupt: SP  SP – 1 M[SP]  PC SP  SP – 1 M[SP]  PSR –PSR is processor status register EI  0 INTACK  1 PC  IVAD

10 Return Similar  Very similar to return from procedure  Some additional actions PSR holds IE bit PSR holds IE bit Restoring PSR turns interrupts on Restoring PSR turns interrupts on

Exception (from Patterson Hennessey, multicycle MIPS) 11 Just two causes PC – 4 stored Branch to fixed addr Undefined instruction and arithmetic overflow

12 Restarting Instruction?  Imagine the interrupt (exception) was a page fault Need to get the page, and then rerun the instruction Need to get the page, and then rerun the instruction  Keeping instructions simple/short helps out! Otherwise may need to save some intermediate state Otherwise may need to save some intermediate state  Imagine block-move instruction such as the Pentium MOVS –moves/copies an entire string (of variable length) in a single instruction!

Types of I/O Programmed I/O Direct Memory Access (DMA) 13

14 Direct Memory Access (DMA)  Programmed I/O is when CPU reads/writes every word Problem: overhead is high; nothing else getting done on CPU Problem: overhead is high; nothing else getting done on CPU Especially for mass-storage devices like disk Especially for mass-storage devices like disk  DMA: Let device controller read/write directly to memory CPU goes about its usual business of executing other instructions CPU goes about its usual business of executing other instructions  typically cannot access memory while DMA is going on! Challenges? Challenges?

15Protocol  DMA protocol DMA device takes over main bus DMA device takes over main bus Becomes bus master Becomes bus master Asserts addresses Asserts addresses Basically interfaces to memory or memory controller Basically interfaces to memory or memory controller

How?  DMA device requests bus (assert BR)  CPU grants request (assert BG)  CPU takes its signals to Hi-Z now DMA can use its signals to connect with memory now DMA can use its signals to connect with memory no conflict with CPU’s signals (they are floating) no conflict with CPU’s signals (they are floating) 16

Transfer Modes  Several types of transfer modes Continuous: DMA controller transfers all data (say a disk sector) at once Continuous: DMA controller transfers all data (say a disk sector) at once  As many memory cycles as data Burst: DMA controller cycle steals, takes a cycle at end of every CPU instruction Burst: DMA controller cycle steals, takes a cycle at end of every CPU instruction  Note: today’s processors are more sophisticated there is a memory controller (“Northbridge”) there is a memory controller (“Northbridge”) sits in-between CPU and memory sits in-between CPU and memory Why? Memories are more complex, caches, etc. Why? Memories are more complex, caches, etc. 17

18 End of DMA  Controller needs to inform CPU De-assert BR De-assert BR Then CPU lowers BG and proceeds Then CPU lowers BG and proceeds

19 DMA Controller  Needs typical I/O signals Interrupt request Interrupt request Status of device Status of device  Also needs controls for DMA transfer Memory address Memory address Word count Word count

20 Block Diagram

21 Typical Driver Interface  Software drivers Set the memory address Set the memory address Set word count Set word count Assert “GO” (usually bit in control word) Assert “GO” (usually bit in control word) DMA controller starts copying … DMA controller starts copying … … and requests interrupt when transfer complete … and requests interrupt when transfer complete

Trends in Communications  Older bus standards, such as ISA and PCI, were parallel (conventional “bus”)  Newer (PCI Express) use serial channels (lanes) So slots for slower devices can be x1 So slots for slower devices can be x1 Slots for devices such as GPUs can be x16 (max x32 in spec) Slots for devices such as GPUs can be x16 (max x32 in spec) lane PCI-E (below) 1 lane (right)

Disks  Change from ATA/IDE to SATA IDE had 16 data channels IDE had 16 data channels SATA has 2 twisted pair (xmit and recv) SATA has 2 twisted pair (xmit and recv) 23

24RS-232/UART  Called “Asynchronous” But both sides have precise clocks But both sides have precise clocks Agree on speed Agree on speed Receiver syncs during start bit Receiver syncs during start bit

25USB  One master The PC The PC  Idea was to have thin cables and plug and play  Specs include hardware and software We only cover hardware We only cover hardware

26 USB – Packet serial I/O  Four wires total  +5v and GND  Two signal wires Twisted pair Twisted pair Differential signaling Differential signaling Differential 1 is D+ > 2.8v and D- 2.8v and D- < 0.3v Differential 0 is opposite Differential 0 is opposite Also a single-ended zero when D+ & D- low (end of packet, reset, disconnect) Also a single-ended zero when D+ & D- low (end of packet, reset, disconnect)

27Speed  Three speeds High is 480 Mb/s High is 480 Mb/s Full is 12 Mb/s Full is 12 Mb/s Low is 1.5 Mb/s Low is 1.5 Mb/s New Super Speed, 5Gb/s!! New Super Speed, 5Gb/s!!  Pull-up indicates full/low  High speed starts as full, then handshakes and transitions  High and low speeds interpret zeros and ones inverted.

28Coding  NRZI Non-Return to Zero Inverted Non-Return to Zero Inverted Transition if sending 0, none if sending 1 Transition if sending 0, none if sending 1  Bit stuffing Since a string of 1s causes no transitions, synchronization may be lost Since a string of 1s causes no transitions, synchronization may be lost A zero is stuffed in after six consecutive ones A zero is stuffed in after six consecutive ones  Sync field Each packet starts with a sync Each packet starts with a sync 8 bits: bits:

29Packets  Won’t go into details

Summary  Many types of I/O memory-mapped is most common memory-mapped is most common  different devices given different address ranges many different device protocols many different device protocols  PS/2: keyboard, mice  RS-232: serial ports  USB: most common today  also Firewire, Thunderbolt, …  ethernet also monitors, displays also monitors, displays  we did VGA (other higher resolutions also possible)  DVI is most common today 30

Conclusion of this course  What did we learn this semester? Combinational logic Combinational logic Sequential logic, finite-state machines Sequential logic, finite-state machines Basic building blocks Basic building blocks  registers, counters  adders, subtractors, ALUs  memories, and memory-mapped I/O  datapaths Verilog Verilog  hierarchical design  display interfaces, input devices, debouncing CPUs CPUs  single-cycle, multicycle  pipelining, hazards, forwarding, stalling  Built an entire MIPS CPU! 31

Some Tips for your final project  Use MARS to assemble your program! use:.text 0x use:.text 0x  then simply copy all the machine code into your project  SLT if you want to implement SLT, talk to me! if you want to implement SLT, talk to me!  BEQ, BNE make sure “delayed branching” is off in MARS make sure “delayed branching” is off in MARS  J  JAL, JR not necessary, but could simplify your code not necessary, but could simplify your code  if you want to use procedure calls PC=PC+4 (not 8) because our MIPS is unpipelined, no delayed jumps PC=PC+4 (not 8) because our MIPS is unpipelined, no delayed jumps 32

Timeline  April 19 (Thu): Test #1 graded, ready for pickup Test #1 graded, ready for pickup  April 20 (Fri): First set of final project demos First set of final project demos HW #2 due HW #2 due Test #2 (take home) released Test #2 (take home) released  April 23 (Mon): Tentative grades for those already demo’ed Tentative grades for those already demo’ed Second set of final project demos Second set of final project demos Hw #2 due (last chance) Hw #2 due (last chance)  April 25 (Wed): Tentative grades for those already demo’ed Tentative grades for those already demo’ed Last chance to demo final project Last chance to demo final project 33