Digital System Design Verilog ® HDL Behavioral Modeling Maziar Goudarzi

Objectives of this Topic initial and always blocks The concept of multiple flows of control Practice simple examples Procedural assignment vs. Continuous assignment Conditional statements – if, case, casex, casez Loop statements – while, for, repeat, forever 2010DSD2

Introduction The move toward higher abstractions – Gate-level modeling Netlist of gates – Dataflow modeling Boolean function assigned to a net – Now, behavioral modeling A sequential algorithm (quite similar to software) that determines the value(s) of variable(s) 2010DSD3

Structured Procedures Two basic structured procedure statements always initial – All behavioral statements appear only inside these blocks – Each always or initial block has a separate activity flow (multithreading, concurrency) – Start from simulation time 0 – No nesting 2010DSD4

Structured Procedures: initial statement Starts at time 0 Executes only once during a simulation Multiple initial blocks, execute in parallel – All start at time 0 – Each finishes independently Syntax: initial begin // behavioral statements end 2010DSD5

Structured Procedures: initial statement (cont’d) module stimulus; reg x, y, a, b, m; initial m= 1’b0; initial begin #5 a=1’b1; #25 b=1’b0; end initial begin #10 x=1’b0; #25 y=1’b1; end initial #50 $finish; endmodule 2010DSD6 Example:

Initializing variables Ordinary style, using initial block reg clock; initial clock = 0; Combined declaration and initialization reg clock = 0; // RHS must be constant module adder ( output reg [7:0] sum = 0, output reg co = 0, input [7:0] a, b, input ci);... endmodule 72010DSD

Structured Procedures: always statement Start at time 0 Execute the statements in a looping fashion Example 2010DSD8

Procedural Assignments Assignments inside initial and always To update values of “register” data types – The value remains unchanged until another procedural assignment updates it – Compare to continuous assignment (Dataflow Modeling, previous chapter) 2010DSD9

Procedural Assignments (cont’d) Syntax = – can be reg, integer, real, time A bit-select of the above (e.g., addr[0] ) A part-select of the above (e.g., addr[31:16] ) A concatenation of any of the above – is the same as introduced in dataflow modeling – What happens if the widths do not match? LHS wider than RHS => RHS is zero-extended RHS wider than LHS => RHS is truncated (Least significant part is kept) 2010DSD10

Behavioral Modeling Statements: Conditional Statements Just the same as if-else in C Syntax: if ( ) true_statement; else false_statement; if ( ) true_statement1; else if ( ) true_statement2; else if ( ) true_statement3; else default_statement; True is 1 or non-zero False is 0 or ambiguous ( x or z ) More than one statement: begin end 2010DSD11

Behavioral Modeling Statements: Multiway Branching Similar to switch-case statement in C Syntax: case ( ) alternative1: statement1; alternative2: statement2;... default: default_statement; // optional endcase Notes: – is compared to the alternatives in the order specified. – Default statement is optional 2010DSD12

Multiway Branching (cont’d) Examples: To be provided in the class Now, you write a 4-to-1 multiplexer. 2010DSD13

Multiway Branching (cont’d) The case statements compare and alternatives bit-for-bit – x and z values should match 2010DSD14 module demultiplexer1_to_4(out0, out1, out2, out3, in, s1, s0); output out0, out1, out2, out3; input in, s1, s0; or s0 or in) case( {s1, s0} ) 2’b00: begin... end 2’b01: begin... end 2’b10: begin... end 2’b11: begin... end 2’bx0, 2’bx1, 2’bxz, 2’bxx, 2’b0x, 2’b1x, 2’bzx: begin... end 2’bz0, 2’bz1, 2’bzz, 2’b0z, 2’b1z: begin... end default: $display(“Unspecified control signals”); endcase endmodule

Multiway Branching (cont’d) casex and casez keywords – casez treats all z values as “don’t care” – casex treats all x and z values as “don’t care” Example: To be provided in the class 2010DSD15

Behavioral Modeling Statements: Loops Loops in Verilog – while, for, repeat, forever The while loop syntax: while ( ) statement; 2010DSD16

while Loop Example To be provided in the class 2010DSD17

Loops (cont’d) The for loop – Similar to C – Syntax: for( init_expr; cond_expr; change_expr) statement; – Example: Provided in the class 2010DSD18

Loops (cont’d) The repeat loop – Syntax: repeat( number_of_iterations ) statement; – The number_of_iterations expression is evaluated only when the loop is first encountered integer count; initial begin count = 0; repeat(128) begin $display("Count = %d", count); count = count + 1; end

Loops (cont’d) The forever loop – Syntax: forever statement; – Equivalent to while(1) 2010DSD20

Have your learned this topic What is behavioral modeling What are the Verilog constructs for behavioral modeling Statements used in behavioral modeling – Conditional – Multiway branching – Loops 2010DSD21

Objectives of This Topic Internal operations of Event-Driven simulators Behavioral Modeling (cont’d) – Blocking vs. non-blocking assignments – Race condition – Timing control by delays, events, and level – Other features 2010DSD22

Two Types of Simulators Oblivious Simulators – Evaluate outputs repetitively at predefined time intervals Event Driven Simulators – Evaluate outputs only when an event occurs on the inputs 2010DSD23

Internal Operations of Event-Driven Simulators Event Transaction The simulation cycle 2010DSD24

Blocking Procedural Assignments The two types of procedural assignments – Blocking assignments – Non-blocking assignments Blocking assignments – are executed in order (sequentially) – Example: reg x, y, z; reg [15:0] reg_a, reg_b; integer count; initial begin x=0; y=1; z=1; count=0; reg_a= 16’b0; reg_b = reg_a; #15 reg_a[2] = 1’b1; #10 reg_b[15:13] = {x, y, z}; count = count + 1; end 2010DSD25 All executed at time 0 All executed at time 25 executed at time 15

Non-Blocking Procedural Assignments Non-blocking assignments – Processing of the next statements is not blocked for this one – Transactions created sequentially (in order), but executed after all blocking assignments in the corresponding simulation cycle – Syntax: – Example: reg x, y, z; reg [15:0] reg_a, reg_b; integer count; initial begin x=0; y=1; z=1; count=0; reg_a= 16’b0; reg_b = reg_a; reg_a[2] <= #15 1’b1; reg_b[15:13] <= #10 {x, y, z}; count <= count + 1; end 2010 All executed at time 0 Scheduled to run at time 15 Scheduled to run at time 10

Non-Blocking Assignments (cont’d) Application of non-blocking assignments – Used to model concurrent data transfers – Example: Write behavioral statements to swap values of two variables clock) begin reg1 <= #1 in1; reg2 clock) in2 ^ in3; reg3 <= #1 reg1; end 2010DSD27 The old value of reg1 is used

Race Condition When the final result of simulating two (or more) concurrent processes depends on their order of execution Example: clock) b = a; clock) a = b; Solution: clock) b <= a; clock) a <= b; 2010DSD28 clock) begin temp_b = b; temp_a = a; b = temp_a; a = temp_b; end

Race Condition (cont’d) Recommendation – Concurrent data transfers => race condition – Use non-blocking assignments for concurrent data transfers – Example: pipeline modelling – Disadvantage: Lower simulation performance Higher memory usage in the simulator 2010DSD29

Timing Controls in Behavioral Modeling

Introduction No timing controls  No advance in simulation time Three methods of timing control – delay-based – event-based – level-sensitive 2010DSD31

Delay-based Timing Controls Delay  Duration between encountering and executing a statement Delay symbol: # Delay specification syntax: #5 #(1:2:3) 2010DSD32

Delay-based Timing Controls (cont’d) Types of delay-based timing controls 1. Regular delay control 2. Intra-assignment delay control 3. Zero-delay control 2010DSD33

Regular Delay Control Symbol: non-zero delay before a procedural assignment 2010DSD34

Intra-assignment Delay Control Symbol: non-zero delay to the right of the assignment operator Operation sequence: 1. Compute the RHS expression at current time. 2. Defer the assignment of the above computed value to the LHS by the specified delay. 2010DSD35

Zero-Delay Control Symbol: #0 Different initial/always blocks in the same simulation time – Execution order non-deterministic #0 ensures execution after all other statements – Eliminates race conditions (only in simulation) Multiple zero-delay statements – Non-deterministic execution order 2010DSD36

Event-based Timing Control Event – Change in the value of a register or net – Used to trigger execution of a statement or block (reactive behavior/reactivity) Types of Event-based timing control 1. Regular event control 2. Named event control 3. Event OR control 2010DSD37

Regular Event Control ) Events to specify: – posedge sig Change of sig from any value to 1 or from 0 to any value – negedge sig Change of sig from any value to 0 or from 1 to any value – sig Any change in sig value 2010DSD38

Named Event Control You can declare (name) an event, and then trigger and recognize it. Keyword: event event calc_finished; Verilog symbol for triggering: -> ->calc_finished Verilog symbol 2010DSD39

Event OR control Used when need to trigger a block upon occurrence of any of a set of events. The list of the events: sensitivity list Keyword: or 2010DSD40

Event OR control Simpler syntax – reset, clock, d) 2010DSD41

Level-sensitive Timing Control Level-sensitive vs. event-based – event-based: wait for triggering of an event (change in signal value) – level-sensitive: wait for a certain condition (on values/levels of signals) Keyword: wait() always wait(count_enable) #20 count=count+1; 2010DSD42

Have you learned this topic? Race conditions – Blocking vs. non-blocking assignments – Zero delay control Timing control in behavioral statements – Required to advance the simulation time – Different types Delay-based Event-based Level-sensitive 2010DSD43

Objectives of This Topic Some more constructs on Behavioral Modeling – Parallel blocks – Nested blocks – disable keyword Verilog® Scheduling Semantics 2011DSD44

Blocks, Sequential blocks Used to group multiple statements Sequential blocks – Keywords: begin end – Statements are processed in order. – A statement is executed only after its preceding one completes. Exceptions: non-blocking assignments and intra-assignment delays – A delay or event is relative to the simulation time when the previous statement completed execution 2011DSD45

Parallel Blocks – Keywords: fork, join – Statements in the blocks are executed concurrently – Timing controls specify the order of execution of the statements – All delays are relative to the time the block was entered The written order of statements is not important The join is done when all the parallel statements are finished 2011DSD46

Sequential vs. Parallel Blocks initial begin x=1’b0; #5y=1’b1; #10z={x,y}; #20w={y,x}; end initial fork x=1’b0; #5y=1’b1; #10z={x,y}; #20w={y,x}; join DSD472011

Parallel Blocks and Race Parallel execution  Race conditions may arise initial fork x=1’b0; y=1’b1; z={x,y}; w={y,x}; join z,w can take either 2’b01, 2’b10 or 2’bxx, 2’bxx or other combinations depending on simulator 2011DSD48

Special Features of Blocks Contents – Nested blocks – Named blocks – Disabling named blocks 2011DSD49

Nested Blocks Sequential and parallel blocks can be mixed initial begin x=1’b0; fork #5 y=1’b1; #10 z={x,y}; join #20w={y,x}; end 2011DSD50

Named blocks Syntax: begin: fork: … endjoin Advantages: – Can have local variables (local variables are static) – Are part of the design hierarchy. – Their local variables can be accessed using hierarchical names – Can be disabled 2011DSD51

Disabling Named Blocks Keyword: disable Action: – Similar to break in C/C++, but can disable any named block not just the inner-most block. 2011DSD52

Behavioral Modeling Some Examples

4-to-1 Multiplexer 2011DSD54

4-bit Counter 2011DSD55

Have you learned this topic? Sequential and Parallel Blocks Special Features of Blocks – Nested blocks – Named blocks – Disabling named blocks 2011DSD56

Objectives of This Topic Use Tasks and Functions for better structured code 2010DSD57

Introduction Procedures/Subroutines/Functions in SW programming languages – The same functionality, in different places Verilog equivalence: – Tasks and Functions – Used in behavioral modeling – Part of design hierarchy  Hierarchical name 2010DSD58

Functions Keyword: function, endfunction Can be used if the procedure – does not have any timing control constructs – returns exactly one single value – has at least one input argument 2010DSD59

Function Declaration Syntax function ; input // at least one input // optional begin // if more than one statement needed end // if begin used endfunction 2010DSD60

Function Invocation Syntax ( ); Example: function my_not; input in; my_not= ~in; endfunction reg ni; initial ni = my_not(i); 2010DSD61

Function Semantics – much like function in Pascal – An internal implicit reg is declared inside the function with the same name – The return value is specified by setting that implicit reg – defines width and type of the implicit reg can be integer or real default bit width is DSD62

Two Function Examples: Parity Generator, and Controllable Shifter 2010DSD63

Tasks Keywords: task, endtask Must be used if the procedure has – any timing control constructs – zero or more than one output arguments – no input arguments 2010DSD64

Task Declaration Syntax task ; // optional begin // if more than one statement needed end // if begin used! endtask 2010DSD65

Task Invocation Syntax ; ( ); – input and inout arguments are passed into the task – output and inout arguments are passed back to the invoking statement when task is completed 2010DSD66

I/O declaration in modules vs. tasks – Both use keywords: input, output, inout – In modules, represent ports connect to external signals – In tasks, represent arguments pass values to and from the task 2010DSD67

Task Examples Use of input and output arguments Use of module local variables 2010DSD68

Automatic Tasks and Functions Used for re-entrant code – Task called from multiple locations – Recursive function calls Keyword – automatic Example function automatic integer factorial; task automatic bitwise_xor; 2010DSD69

Automatic Function Example Factorial 2010DSD70

Tasks and Functions Differences between Tasks and Functions

Differences between... Functions – Can enable (call) just another function (not task) – Execute in 0 simulation time – No timing control statements allowed – At least one input – Return only a single value Tasks – Can enable other tasks and functions – May execute in non-zero simulation time – May contain any timing control statements – May have arbitrary input, output, or inout – Do not return any value 2010DSD72

Have you learned this topic? How to define tasks and functions Where to use each of them – The same purpose as subroutines in SW – Provide more readability, easier code management – Are part of design hierarchy – Tasks are more general than functions Can represent almost any common Verilog code – Functions can only model purely combinational calculations 2010DSD73