1. Spring 2007W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406Slide 1 ECE 406 – Design of Complex Digital Systems Lecture 7: Design Example, Modeling Flip-Flops Spring 2007 W. Rhett Davis NC State University with significant material from Paul Franzon, Bill Allen, & Xun Liu

2. Spring 2007W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406Slide 2 Conditional Statements: if-else if - else if - else has the following syntax. if ( ) ; else if ( ) ; else ; If the logical value of is true, is executed. If the logical value of is false and the logical value of is true then is executed. If the logical values of both and are false, then is executed. Sutherland guide 10.3

3. Spring 2007W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406Slide 3 ALU Example: if-else Code fragment of a 16-bit arithmetic logic unit (ALU) that performs one of 5 operations. if (alu_ctrl == 0) // alu_ctrl is 3 bits ALU_OUT = ALU_IN1 + ALU_IN2;// add else if (alu_ctrl == 1) ALU_OUT = ALU_IN1 - ALU_IN2;// subtract else if (alu_ctrl == 2) ALU_OUT = ALU_IN1 & ALU_IN2;// and else if (alu_ctrl == 3) ALU_OUT = ALU_IN1 | ALU_IN2;// or else if (alu_ctrl == 4) ALU_OUT = ALU_IN1 ^ ALU_IN2;// exor else ALU_OUT = 16’d0;// other 3 undefined

4. Spring 2007W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406Slide 4 Conditional Statements: case The syntax of the case statement is: case ( ) : ; : ; default: ; endcase The value of is matched to in sequence, For the first that matches, the corresponding is executed. If no alternatives match, is executed. Sutherland guide 10.3

5. Spring 2007W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406Slide 5 ALU Example: case Using the previous example of an ALU, the corresponding implementation using a case statement is: case (alu_ctrl) 3’d0: ALU_OUT = ALU_IN1 + ALU_IN2; 3’d1: ALU_OUT = ALU_IN1 - ALU_IN2; 3’d2: ALU_OUT = ALU_IN1 & ALU_IN2; 3’d3: ALU_OUT = ALU_IN1 | ALU_IN2; 3’d4: ALU_OUT = ALU_IN1 ^ ALU_IN2; default: ALU_OUT = 16’d0;

6. Spring 2007W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406Slide 6 case: Comparison Details The case statement literally compares 0, 1, x and z values in the conditional expression bit-by-bit with the alternatives. Thus if the case expression is 4’b10xz, the comparison is looking for an alternative of 4’b10xz. In other words an exact match is required. Also, if the sizes of the evaluated expression and the alternative pattern are unequal, the shortest field is extended with zeros so the sizes are equal.

7. Spring 2007W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406Slide 7 Alternatives: casex, casez There are two variants of the case statement defined by the keywords casex and casez. casex treats all x and z values in the case expression or alternatives as don’t cares. casez treats all z values in the case expression or alternatives as don’t care’s. The casex is useful when the state of certain bit positions is immaterial in some of the alternatives. By using casex in such situations, it is possible to reduce the number of alternatives needed. Sutherland guide 10.3

8. Spring 2007W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406Slide 8 Procedural Examples l Muxes and Data Selectors reg [1:0] in1, in2, out; reg in3; always@(in1 or in2 or in3) if (in3) out = in1; else out = in2; in1[0] in2[0] in1[1] in2[1] in3 out[0] out[1] 1010 in1[0] in1[1] in1[2] in1[3] in2 01230123 out reg [3:0] in1; regout; reg [1:0] in2; always@(in1 or in2) case (in2) 2’b00 : out = in1[0]; 2’b01 : out = in1[1]; 2’b10 : out = in1[2]; 2’b11 : out = in1[3]; endcase

9. Spring 2007W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406Slide 9 Procedural Examples l Priority Selector or Encoder always@(A or B or C) casex(A) 3’b1xx : out = B; 3’b01x : out = C; default : out = 2’b0; endcase l Decoder always@(address) case (address) 2’b00 : line = 4’b0001; 2’b01 : line = 4’b0010; 2’b10 : line = 4’b0100; 2’b11 : line = 4’b1000; endcase

10. Spring 2007W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406Slide 10 Latches l Complete the behavior below: always@(clock or D) if (clock) Q = D; clock D Q l We will not intentionally build latches in this class l Instead, we’ll stick to one type of timing element (edge triggered flip-flops)

11. Spring 2007W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406Slide 11 Inferred (Unintentional) Latches l What is happening here? always@(A or B or C) begin D = B & C; if (D) E = C; end

12. Spring 2007W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406Slide 12 Procedural Examples l What about this? always@(A or B) casex (A) 2’b00 : C = B; 2’b01 : C = ~B; endcase

13. Spring 2007W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406Slide 13 Procedural Examples l Will this simulate correctly? always@(A) C = A | B;

14. Spring 2007W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406Slide 14 D Flip-Flop Timing Diagram D clock Q D Q Don’t know (Don’t care) “x” Glitches at input do not appear at output. F/F only samples ‘D’ at positive clock edge.

15. Spring 2007W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406Slide 15 D Flip-Flop Verilog Description D clock Q module flipflop (D, clock, Q); input D, clock; output Q; reg Q; always@(posedge clock) Q = D; endmodule posedge & negedge are keywords Could also be written as Q <= D; (what’s the difference?)

16. Spring 2007W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406Slide 16 Blocking vs. Non Blocking l = is referred to as a blocking assignment, because execution of subsequent code is blocked until the assignment is made. l <= is referred to as non- blocking assignment. Essentially, all non-blocking right-hand-sides are evaluated but no assignments are made until the end of the procedural block. l Example: What’s the difference between the two code fragments to the right? T&M 1.3.3, Sutherland guide 10.2 always@(posedge clk) begin A = Y; B = A; end always@(posedge clk) begin A <= Y; B <= A; end

17. Spring 2007W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406Slide 17 Inferring Hardware from Assignments l When given an always@(posedge clock) behavior and asked to draw a schematic, I follow these steps: » For every left-hand side of an assignment, draw a flip-flop whose output is connected to that signal » For non-blocking assignments (<=), set the input of each flip-flop to be the right-hand side of the last assignment for each variable » For blocking assignments (=), work back from the end to figure out the inputs to the flip-flops l When writing your own behavior, it is suggested that you use non-blocking assignments (<=), so that you don’t have to work back from the end.

18. Spring 2007W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406Slide 18 Blocking vs. Non Blocking What hardware would be synthesized for this example? A = Y; B = A; A <= Y; B <= A;

19. Spring 2007W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406Slide 19 Example reg A, B, C, D; always@(posedge clock) begin C = A; B = C; C = D; end

20. Spring 2007W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406Slide 20 Example reg A, B, C, D; always@(posedge clock) begin C <= A; B <= C; C <= D; end

21. Spring 2007W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406Slide 21 Example reg A, B, C, D; always@(posedge clock) begin if (A) D <= B; else D <= C; C <= D; end

22. Spring 2007W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406Slide 22 Procedural Examples l Is there anything wrong with this code? always@(A or B) casex (A) 2’b00 : C = B; 2’b01 : C = ~B; endcase

23. Spring 2007W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406Slide 23 Design Example l Design a module named “ALU”. l It has three 3-bit inputs A, B, and C and a 1-bit input E. l It has a 3-bit output R and a 1-bit output O. l When E is 1, » R is the bit-wise XOR of A and B, and » O is 1. l When E is 0, » R is the sum of B and C (both are assumed to be signed integers), and » O is the non-overflow indicator, which is 0 when signed overflow happens.

24. Spring 2007W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406Slide 24 A Word About Overflow l Unsigned Overflow occurs when Carry-Out is 1 l Signed Overflow occurs when » the sum of positive numbers is negative OR » the sum of negative numbers is positive …or, equivalently… » the MSBs of the operands are equal AND » the MSB and Carry-Out of the result differ

25. Spring 2007W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406Slide 25 Design Example l Draw a schematic to represent the hardware

26. Spring 2007W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406Slide 26 Design Example l Write the Verilog module using Data-Flow (continuous assignments) ONLY.

27. Spring 2007W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406Slide 27 Design Example l Write a procedural Verilog description (with always @).

28. Spring 2007W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406Slide 28 Summary l How do you model a flip-flop? l What is the difference between blocking and non-blocking assignments? l How do you infer flip-flops for an always@(posedge clock) procedure with blocking or non-blocking assignments? l Is it better to use blocking or non-blocking assignments in an always@(posedge clock) procedure? Why?