PROJECT - ZYNQ Yakir Peretz Idan Homri Semester - winter 2014 Duration - one semester

PROJECT GOALS  Creating a system that enables reading images from an external device, saving it in the memory and displaying it by RGB.  Creating a programmable logic design that will handle the transportation of the data from the main memory to the output via video direct mapped accessed (VDMA) component.

WHAT WAS DONE SO FAR  Learning the VIVADO tool – IP generator, synthesis, implementation and simulation using the labs provided by xilinx.  Learning the SDK environment – software part of the project. Writing C/C++ code to check and debug the hardware (in progress).  Understanding the implementation of the components being used in the PL side:  Learning the VDMA, video timing controller, stream to video into details:  Concept – understanding the way the unit works, and what are the parts we will use for our project  Interface – understand the purpose and use of each port, and define the ports we will use.  Connection with the other units.  Creating the system – connect all components into a system  Learning the format in which the picture is saved in the memory, and the transformation to an RGB format (in progress).

BLOCK DIAGRAM AXI stream

GENERAL EXPLANATION FOR THE DATA TRANSFER 1. The data is loaded from an external device, connected to a UART input on the board. 2. The UART input is connected to the processor. With a matlab code we are reading the data sent to the UART and saving it in a buffer. Since the data is now saved in the program and we want it to be in a specific location in the DDR memory, we now write it to the physical location in VHDL code. 3. Now the ZYNQ processor is triggering the VDMA by sendin the start address of the data in the memory, and the size on an AXI_LITE. 4. The data is then being transferred to the VDMA and saved in a frame buffer, ready to be streamed to the output. The transportation of the data is executed using the memory controller and the VDMA on an AXI4 bus, thus much faster since there is no need for processor intervention. 5. The ARM is responsible for supplying the signals for the operation initialization and the information regarding the size and address of the data. This is done on the AXI-lite bus

5. The VDMA then outputs the data to a stream to video out component that is responsible for the streaming of the data in a RGB format. 6. The responsibility for timing this whole process is on the “video timing controller”. This is a component that gets input signals regarding the starting of a transfer, and generates sync signals to the components in order to enable a correct data transfer. 7. Once the operation of tranfering a frame is done the processor receives a signal from the VDMA, telling him that this data transfer is over with.

THE CONCEPT BEHIND THE DATA FLOW  The data that is going thru our system is making a long way before getting to the output port. Why is that, and why isn’t it connected directly?  the transportation of the data from an external device is very slow, and we probably wont be able to see a movie that way.  With that said, the data should be saved in an internal memory, and then go out, since the communication with this memory is much faster.  Why then, do we need the VDMA component?  Since the memory is not always available to communicate with our process, we save it in the buffer on the VDMA, and then transfer it out thru a stream to video out component.  The stream to video out is responsible for taking our data and generate the frame in the wanted format. Meaning taking the data saved as pixels in one way and display it in our way (RGB).

FULL SYSTEM VIEW Axi 4 Axi stream Axi lite

PS SIDE OVERVIEW To VDMA via Axi lite To VDMA via AXI-4

CLOCKS IN THE SYSTEM  The system is working with 3 busses to transfer data:  AXI4 – to transfer the data from the memory to the VDMA, controlled by the memory controller.  AXI4 – lite – for communication between the processor and the VDMA regarding the control and status of the data transfer.  AXI4 – stream – to transfer the data that is saved in the VDMA to the output thru the “AXI stream to video out” component  Each of this busses is working with it’s own clock. Thus we have 3 potential clocks in the design.  The clocks are generated in the PS side and supplied to the system.  Since the VDMA is connected to all 3 buses it has 3 ports for that purpose. That way by defining the clocks frequencies we can control the data flow.

EXCEPTIONS  For the flow to work correctly we must set the memory mapped side of the VDMA to work faster then the streaming side.  The clock of the AXI_Lite must be <= AXI4  those are exceptions defined by the VDMA user guide

REGISTER DEFINITIONS  VDMA – page16 and on  Video timing controller – page 30 and on

GANT