Design Methodology Based on VHDL Instructors: Fu-Chiung Cheng ( 鄭福炯 ) Associate Professor Computer Science & Engineering Tatung University

Outline ELEMENTS OF VHDL TOP-DOWN DESIGN Verification DESIGN WITH VHDL

VHDL Interface specification Format: ENTITY component_name IS input and output ports. physical and other parameters. END component_name; Example: ENTITY mux2_1 IS GENERIC (dz_delay : TIME := 6 NS); PORT (sel, data1, data0 : IN BIT; z : OUT BIT); END mux2_1;

VHDL architectural specifications Format: ARCHITECTURE identifier OF component_name IS declarations. BEGIN specification of the functionality of the component in terms of its input lines and influenced by physical and other parameters. END identifier;

VHDL architectural specifications Example: ARCHITECTURE dataflow OF mux2_1 IS BEGIN z <= data1 AFTER dz_delay WHEN sel = '1' ELSE data0 AFTER dz_delay; END dataflow;

Multiple architectural specifications

Packages Format PACKAGE package_name IS component declarations. sub-program declarations. END package_name; PACKAGE BODY package_name IS type definitions. sub-programs. END package_name;

Design binding LIBRARY library_name; CONFIGURATION configuration_name OF component_name IS binding of Entities and Architectures. specifying parameters of a design. binding components of a library to subcomponents. END CONFIGURATION;

Recursive partition procedure Top-down Design Partition Algorithm: Partition (system) IF HardwareMappingOf (system) IS done THEN SaveHardwareOf (system) ELSE FOR EVERY Functionally-Distinct part_i OF system Partition (part_i); END FOR; END IF; END Partition;

Top-down design, bottom-up implementation SUD: System Under Design SSC: System Sub-Component Shaded areas designate sub-components with hardware implementation.

Verifying the first level of partitioning Verification of High level functions

Verifying hardware implementation Partial Hardware, Partial Behavioral Model

Verifying the final design Partial Hardware, Partial Behavioral Model Too time consuming?

Verifying hardware implementation of SSC3 Verify sub-part in hardware

Verifying the final design Back annotation: SSC3 is a behavioral model with physical information(such as timing,..)

VHDL Design Example Serial adder: Synchronously add data on a and b and put result on result. See Fig 3.12 on page 41 Design tool: available synthesis tool Available Design In this example, assume that we can use only multiplexer and d-flip/flop components

Available library elements Multiplexer Flipflop See Fig 3.13 on page 43 Each component: – Interface description – Architectural description New design component can be reused

Multiplexer library element ENTITY mux2_1 IS GENERIC (dz_delay : TIME := 6 NS); PORT (sel, data1, data0 : IN BIT; z : OUT BIT); END mux2_1; -- ARCHITECTURE dataflow OF mux2_1 IS BEGIN z <= data1 AFTER dz_delay WHEN sel = '1' ELSE data0 AFTER dz_delay; END dataflow;

ENTITY flop IS GENERIC (td_reset, td_in : TIME := 8 NS); PORT (reset, din, clk : IN BIT; qout : BUFFER BIT := '0'); END flop; ARCHITECTURE behavioral OF flop IS BEGIN PROCESS (clk) BEGIN IF (clk = '0' AND clk'EVENT) THEN IF reset = '1' THEN qout <= '0' AFTER td_reset; ELSE qout <= din AFTER td_in; END IF; END PROCESS; END behavioral; Flip-flop library element.

Behavioral and Dataflow Description Dataflow descriptions see Fig 3.15 Behavioral descriptions see Fig3.17

Divide by 8, counter ENTITY counter IS GENERIC (td_cnt : TIME := 8 NS); PORT (reset, clk : IN BIT; counting : OUT BIT := '0'); CONSTANT limit : INTEGER := 8; END counter; ARCHITECTURE behavioral OF counter IS BEGIN next page; END behavioral;

PROCESS (clk) VARIABLE count : INTEGER := limit; BEGIN IF (clk = '0' AND clk'EVENT) THEN IF reset = '1' THEN count := 0; ELSE IF count < limit THEN count := count + 1; END IF; END IF; IF count = limit THEN counting <= '0' AFTER td_cnt; ELSE counting <= '1' AFTER td_cnt; END IF;

Design stage setting. See Fig 3.19 on page 49 Synthesis tool – Input: VHDL – Output: CMOS layout Available Libraries: – System library: mux2-1 and Flip/Flop – Pre-designed Library: Counter

Serial adder VHDL behavioral description. ENTITY serial_adder IS PORT (a, b, start, clock : IN BIT; ready : OUT BIT; result : BUFFER BIT_VECTOR (7 DOWNTO 0)); END serial_adder; -- ARCHITECTURE behavioral OF serial_adder IS BEGIN next page; END behavioral;

PROCESS (clock) VARIABLE count : INTEGER := 8; VARIABLE sum, carry : BIT; BEGIN IF (clock = '0' AND clock'EVENT) THEN IF start = '1' THEN count := 0; carry := '0'; ELSE IF count < 8 THEN count := count + 1; sum := a XOR b XOR carry; carry := (a AND b) OR (a AND carry) OR (b AND carry); result <= sum & result (7 DOWNTO 1); END IF; IF count = 8 THEN ready <= '1'; ELSE ready <= '0'; END IF; END IF;END PROCESS;

VHDL simulation results Fig 3.21 on page 50 The correct implementation on behavioral description Match “Verifying the first level of partitioning” The next stage: use library components to implement the subsystems. Recursive partitioning:

Recursive partitioning IF count < 8 THEN count := count + 1; sum := a XOR b XOR carry; carry := (a AND b) OR (a AND carry) OR (b AND carry); result <= sum & result (7 DOWNTO 1); END IF; Need flip/flop: carry := …. carry;

General layout of serial_adder See Fig 3.23 on page 52

First level of partitioning See Fig 3.24 on page 52 serial_adder full_adderflip_flopshiftercounter

Full_adder description ENTITY fulladder IS PORT (a, b, cin : IN BIT; sum, cout : OUT BIT); END fulladder; -- ARCHITECTURE behavioral OF fulladder IS BEGIN sum <= a XOR b XOR cin; cout <= (a AND b) OR (a AND cin) OR (b AND cin); END behavioral;

Shifter VHDL description ENTITY shifter IS PORT (sin, reset, enable, clk : IN BIT; parout : BUFFER BIT_VECTOR (7 DOWNTO 0)); END shifter; -- ARCHITECTURE dataflow OF shifter IS BEGIN sh: BLOCK (clk = '0' AND clk'EVENT) BEGIN parout <= " " WHEN reset = '1' ELSE sin & parout (7 DOWNTO 1) WHEN enable = '1' ELSE UNAFFECTED; END BLOCK; END dataflow;

Completed parts of first partitioning See Fig 3.27 on page 53 Shifter is a sequential circuit that cannot be synthesized with our tool setting. serial_adder full_adderflip_flopshiftercounter

Structural description of serial_adder. Once we have the shifter implementation, the serial_adder can be implemented in structural description in the next page. See Fig 3.28 on page 54.

serial_adder interface ENTITY serial_adder IS PORT (a, b, start, clock : IN BIT; ready : OUT BIT; result : BUFFER BIT_VECTOR (7 DOWNTO 0)); END serial_adder;

ARCHITECTURE structural OF serial_adder IS COMPONENT counter IS GENERIC (td_cnt : TIME := 8 NS); PORT (reset, clk : IN BIT; counting : OUT BIT := '0'); END COMPONENT; COMPONENT shifter IS PORT (sin, reset, enable, clk : IN BIT; parout : BUFFER BIT_VECTOR(7 DOWNTO 0)); END COMPONENT; COMPONENT fulladder IS PORT (a, b, cin : IN BIT; sum, cout : OUT BIT); END COMPONENT; COMPONENT flop IS GENERIC (td_reset, td_in : TIME := 8 NS); PORT (reset, din, clk : IN BIT; qout : BUFFER BIT := '0'); END COMPONENT;

-- SIGNAL serial_sum, carry_in, carry_out, counting : BIT; BEGIN u1 : fulladder PORT MAP (a, b, carry_in, serial_sum, carry_out); u2 : flop PORT MAP (start, carry_out, clock, carry_in); u3 : counter PORT MAP (start, clock, counting); u4 : shifter PORT MAP (serial_sum, start, counting, clock, result); u5 : ready <= NOT counting; END structural;

Signal mapping for fulladder instantiation Fig 3.29 on page 55 Signals in structural architecture of serial_adder a b carry_in serial_sum carry_out a b cin sum count Signals in the interface of fulladder

Interconnecting ports. See Fig 3.30 on page 56

Partitioning shifter. A Shifter contains 8 interconnected der_flop See Fig 3.31 page 56

ENTITY der_flop IS PORT (din, reset, enable, clk : IN BIT; qout : OUT BIT := '0'); END der_flop; -- ARCHITECTURE behavioral OF der_flop IS BEGIN PROCESS (clk) BEGIN IF (clk = '0' AND clk'EVENT) THEN IF reset = '1' THEN qout <= '0'; ELSE IF enable = '1' THEN qout <= din; END IF; END PROCESS; END behavioral;

ENTITY shifter IS PORT (sin, reset, enable, clk : IN BIT; parout : BUFFER BIT_VECTOR (7 DOWNTO 0)); END shifter; -- ARCHITECTURE structural OF shifter IS COMPONENT der_flop IS PORT (din, reset, enable, clk : IN BIT; qout : BUFFER BIT := '0'); END COMPONENT; BEGIN b7 : der_flop PORT MAP ( sin, reset, enable, clk, parout(7)); b6 : der_flop PORT MAP (parout(7), reset, enable, clk, parout(6)); b5 : der_flop PORT MAP (parout(6), reset, enable, clk, parout(5)); b4 : der_flop PORT MAP (parout(5), reset, enable, clk, parout(4)); b3 : der_flop PORT MAP (parout(4), reset, enable, clk, parout(3)); b2 : der_flop PORT MAP (parout(3), reset, enable, clk, parout(2)); b1 : der_flop PORT MAP (parout(2), reset, enable, clk, parout(1)); b0 : der_flop PORT MAP (parout(1), reset, enable, clk, parout(0)); END structural;

Hardware realization of der_flop See Fig 3.34 on page 58

Partitioning der_flop. See Fig 3.35 on page 58

ENTITY der_flop IS PORT (din, reset, enable, clk : IN BIT; qout : BUFFER BIT := '0'); END der_flop; -- ARCHITECTURE behavioral OF der_flop IS COMPONENT flop IS GENERIC (td_reset, td_in : TIME := 8 NS); PORT (reset, din, clk : IN BIT; qout : BUFFER BIT); END COMPONENT; COMPONENT mux2_1 IS GENERIC (dz_delay : TIME := 6 NS); PORT (sel, data1, data0 : IN BIT; z : OUT BIT); END COMPONENT; SIGNAL dff_in : BIT; BEGIN mx : mux2_1 PORT MAP (enable, din, qout, dff_in); ff : flop PORT MAP (reset, dff_in, clk, qout); END behavioral;

Complete design of seraial_adder. See Fig 3.37 on page 59

Final Design. See Fig 3.38 on page 60

Subprograms VHDL Subprograms: – procedures and – Functions Subprograms can be declared, defined, and invoked. Values returned or altered by subprograms may or may not have any hardware significance.

Subprograms EX. Functions: – Function for Boolean expression (actual logic) – Function for type conversion (no hardware structure??) Show data to screen from binary to decimal form (no hw) Convert integer to floating point number (yes hw) – Function for delay value calculations (no hardware structure) Subprogram ex: (next page) byte_to_integer. Function ex: fadd

TYPE byte IS ARRAY ( 7 DOWNTO 0 ) OF BIT;... PROCEDURE byte_to_integer (ib : IN byte; oi : OUT INTEGER) IS VARIABLE result : INTEGER := 0; BEGIN FOR i IN 0 TO 7 LOOP IF ib(i) = '1' THEN result := result + 2**i; END IF; END LOOP; oi := result; END byte_to_integer;

fadd (full adder) function. FUNCTION fadd (a, b, c : IN BIT) RETURN BIT_VECTOR IS VARIABLE sc : BIT_VECTOR(1 DOWNTO 0); BEGIN sc(1) := a XOR b XOR c; sc(0) := (a AND b) OR (a AND c) OR (b AND c); RETURN sc; END;

fulladder using fadd. ENTITY fulladder IS PORT (a, b, cin : IN BIT; sum, cout : OUT BIT); END fulladder; -- ARCHITECTURE behavioral OF fulladder IS BEGIN (sum, cout) <= fadd (a, b, cin); END behavioral;

General outline of a controller Fig 3.44 of Page 64 Synchronous style. Finite State Machine: – Current state, current input ==> next state, current output

Moore machine description IF 110 sequence is detected on x THEN z gets '1' ELSE z gets '0' END; X Z clk

Sequence detector state machine. Fig 3.46 on page 65 and below Finite state representation of Fig 3.45 VHDL implementation of 110 sequence detector Reset got get get

ENTITY moore_110_detector IS PORT (x, clk : IN BIT ; z : OUT BIT); END moore_110_detector; -- ARCHITECTURE behavioral OF moore_110_detector IS TYPE state IS (reset, got1, got11, got110); SIGNAL current : state := reset; BEGIN PROCESS(clk) BEGIN next page; END PROCESS; z <= ‘1’ WHEN current = got110 ELSE ‘0’; END behavioral;

PROCESS(clk) BEGIN IF clk = ‘1’ AND clk’EVENT THEN CASE current IS WHEN reset => IF x = ‘1’ THEN current <= got1; ELSE current <= reset; END IF; WHEN got1 => IF x = ‘1’ THEN current <= got11; ELSE current <= reset; END IF; WHEN got11 => IF x = ‘1’ THEN current <= got11; ELSE current <= got110; END IF; WHEN got110 => IF x = ‘1’ THEN current <= got1; ELSE current <= reset; END IF; END CASE; END IF; END PROCESS; z <= ‘1’ WHEN current = got110 ELSE ‘0’;

State transition and corresponding VHDL code … WHEN got1 => IF x='1' THEN current <= got11 ELSE current <= reset; END IF;... Reset got get

VHDL operators. Fig 3.49 Page LOGICAL – Operators : AND OR NAND NOR XOR XNOR – Operand Type : BIT or BOOLEAN – Result Type: BIT or BOOLEAN RELATIONAL – Operators : = /= >= – Operand Type : All Types – Result Type: BOOLEAN

VHDL operators. SHIFT – Operators : SLL SRL SLA SRA ROL ROR – Operand Type : Left: BIT or BOOLEAN Vector Right: INTEGER – Result Type: BOOLEAN ADDING – Operators : + - & – Operand Type : Numeric Array or Array Element – Result Type: Same Type SIGN – Operators : + - – Operand Type : Numeric – Result Type: Same Type

VHDL operators. MULTIPLYING (1) – Operators : * / – Operand Type : INTEGER, REAL – Result Type: Same Type MULTIPLYING (2) – Operators : MOD REM – Operand Type : INTEGER – Result Type: Same Type MISCELLENEOUS – Operators : ** – Operand Type : Left: Numeric Right: Integer – Result Type: Same as Left

Syntax details of the architecture body ARCHITECTURE demo OF example IS SIGNAL a, b, c : BIT := '0'; BEGIN a <= '1' AFTER15NS; b<=NOTaAFTER5NS; c<=aAFTER10NS; END demo; architecture body architecture declarative part s architecture statement part