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CPE 528: Lecture #4 Department of Electrical and Computer Engineering University of Alabama in Huntsville.

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Presentation on theme: "CPE 528: Lecture #4 Department of Electrical and Computer Engineering University of Alabama in Huntsville."— Presentation transcript:

1 CPE 528: Lecture #4 Department of Electrical and Computer Engineering University of Alabama in Huntsville

2 Functions and Procedures Operator Overloading
Outline VHDL operators Functions and Procedures Operator Overloading Multivalued Logic and Signal Resolution IEEE 1164 Standard Logic Generics Generate Statements 02/12/2018 UAH-CPE528

3 VHDL Operators Binary logical operators: and or nand nor xor xnor
Relational: = /= < <= > >= Shift: sll srl sla sra rol ror Adding: + - & (concatenation) Unary sign: + - Multiplying: * / mod rem Miscellaneous: not abs ** Class 7 has the highest precedence (applied first), followed by class 6, then class 5, etc 02/12/2018 UAH-CPE528

4 Example of VHDL Operators
02/12/2018 UAH-CPE528

5 Example of Shift Operators
02/12/2018 UAH-CPE528

6 VHDL Functions Functions execute a sequential algorithm and return a single value to calling program A = “ ” General form 02/12/2018 UAH-CPE528

7 For Loops 02/12/2018 UAH-CPE528

8 Add Function 02/12/2018 UAH-CPE528

9 VHDL Procedures Facilitate decomposition of VHDL code into modules
Procedures can return any number of values using output parameters General form procedure procedure_name (formal-parameter-list) is [declarations] begin Sequential-statements end procedure_name; procedure_name (actual-parameter-list); 02/12/2018 UAH-CPE528

10 Procedure for Adding Bit_vectors
02/12/2018 UAH-CPE528

11 Parameters for Subprogram Calls
02/12/2018 UAH-CPE528

12 Review: Operator Overloading
Operators +, - operate on integers Write procedures for bit vector addition/subtraction addvec, subvec Operator overloading allows using + operator to implicitly call an appropriate addition function How does it work? When compiler encounters a function declaration in which the function name is an operator enclosed in double quotes, the compiler treats the function as an operator overloading (“+”) when a “+” operator is encountered, the compiler automatically checks the types of operands and calls appropriate functions 02/12/2018 UAH-CPE528

13 VHDL Package with Overloaded Operators
02/12/2018 UAH-CPE528

14 Multivalued Logic Bit (0, 1)
Tristate buffers and buses => high impedance state ‘Z’ Unknown state ‘X’ e. g., a gate is driven by ‘Z’, output is unknown a signal is simultaneously driven by ‘0’ and ‘1’ 02/12/2018 UAH-CPE528

15 Tristate Buffers Resolution function to determine the actual value of f since it is driven from two different sources 02/12/2018 UAH-CPE528

16 VHDL signals may either be resolved or unresolved
Signal Resolution VHDL signals may either be resolved or unresolved Resolved signals have an associated resolution function Bit type is unresolved – there is no resolution function if you drive a bit signal to two different values in two concurrent statements, the compiler will generate an error 02/12/2018 UAH-CPE528

17 Signal Resolution (cont’d)
signal R : X01Z := ‘Z’; ... R <= transport ‘0’ after 2 ns, ‘Z’ after 6 ns; R <= transport ‘1’ after 4 ns; R <= transport ‘1’ after 8 ns, ‘0’ after 10 ns; 02/12/2018 UAH-CPE528

18 Resolution Function for X01Z
Define AND and OR for 4-valued inputs? 02/12/2018 UAH-CPE528

19 AND and OR Functions Using X01Z
‘0’ ‘1’ ‘Z’ OR ‘X’ ‘0’ ‘1’ ‘Z’ 02/12/2018 UAH-CPE528

20 IEEE 1164 Standard Logic 9-valued logic system ‘U’ – Uninitialized
‘X’ – Forcing Unknown ‘0’ – Forcing 0 ‘1’ – Forcing 1 ‘Z’ – High impedance ‘W’ – Weak unknown ‘L’ – Weak 0 ‘H’ – Weak 1 ‘-’ – Don’t care If forcing and weak signal are tied together, the forcing signal dominates. Useful in modeling the internal operation of certain types of ICs. 02/12/2018 UAH-CPE528

21 Resolution Function for IEEE 9-valued
02/12/2018 UAH-CPE528

22 AND Table for IEEE 9-valued
02/12/2018 UAH-CPE528

23 AND Function for std_logic_vectors
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24 Example: rise/fall time modeling
Generics Used to specify parameters for a component in such a way that the parameter values must be specified when the component is instantiated Example: rise/fall time modeling 02/12/2018 UAH-CPE528

25 Rise/Fall Time Modeling Using Generics
02/12/2018 UAH-CPE528

26 Generate Statements Provides an easy way of instantiating components when we have an iterative array of identical components Example: 4-bit RCA 02/12/2018 UAH-CPE528

27 4-bit Adder 02/12/2018 UAH-CPE528

28 4-bit Adder using Generate
02/12/2018 UAH-CPE528

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