2. Discussed in class and on Fridays n FSMs (only synchronous, with asynchronous reset) –Moore –Mealy –Rabin-Scott n Generalized register: –With D FFs, –With T FFs, transitions –Iterative circuits (using decomposition to one dimensional, one- directional iterative circuits specified as FSMs) –Trade-off between FSM and iterative circuit –Parallel and serial adder –ALU with arithmetic and logic part. –Realization of all functions of 2 variables –Realization of all symmetric functions. n Generalization of generalized register to SIMD architecture –GAPP processor n Sequential Controller (SAT example) n Pipelined architecture for vector processing n Linear Systolic array for convolution n Generate Statements

3. pipelined Iterative circuit (one dimensional) Finite state machine Iterative circuit (general, n-dimensional) systolic Sequential controller Butterfly combinational Generalized register Data Path SIMD Professor Perkowski wants you to select a good design pattern to get an A in this class and become a talented designer

4. Regular VHDL Structures n Iterative Circuits Are Composed of Many Identical Circuits –Ripple-carry (RC) adder –RAM –Counters –Comparators

5. Generate Statement n Use Generate Statement to Reduce Coding Effort n Can Include Any Concurrent Statement Including Another Generate Statement n Does Not Execute Directly, But Expands into Code Which Does Execute

6. Generate Statement n Automatically Generates Multiple Component Instantiations n Two Kinds of Statements –Iteration »FOR... GENERATE –Conditional »IF... GENERATE

7. Iteration: FOR Generate n Instantiates Identical Components Syntax of FOR identifier : FOR N IN 1 TO 8 GENERATE concurrent-statements END GENERATE name ; –N is a constant and cannot be changed –“name” is required

8. Conditional: IF GENERATE n Takes Care of Boundary Conditions Syntax of IF identifier : IF (boolean expression) GENERATE concurrent-statements END GENERATE name ; –Cannot use “else” or “ifelse” clauses

9. Generate e.g., Ripple Carry (R-C) Adder ENTITY RCAdder_16 IS PORT ( A, B : IN Bit_Vector (15 downto 0); Cforce : IN Bit ; Sum : OUT Bit_Vector(15 downto 0); Cout : OUT Bit ) ; END RCAdder_16 ;

10. Generate e.g., R-C Adder ARCHITECTURE Generate_S OF RCAdder_16 IS COMPONENT Full_Adder --defined elsewhere PORT ( A, B, Cin : IN bit ; S, Cout : OUT bit ); END COMPONENT Full_Adder ; SIGNAL Int_C : BIT_VECTOR (15 DOWNTO 0);

11. Generate e.g., R-C Adder BEGIN --RC Adder All_Bits: FOR I IN 15 DOWNTO 0 GENERATE LSB : IF (I = 0) GENERATE BEGIN S0: Full_Adder PORT MAP ( A(I), B(I), Cforce, Sum(I), Int_C(I) ); END GENERATE S0 ;

12. Generate e.g., R-C Adder Middle_bits: IF ( I 0 ) GENERATE BEGIN SI: Full_Adder PORT MAP ( A(I), B(I), Int_C(I-1), Sum(I), Int_C(I) ); END GENERATE SI;

13. Generate e.g., R-C Adder MSB: IF ( I = 15 ) GENERATE BEGIN S15: Full_Adder PORT MAP ( A(I), B(I), Int_C(I-1), Sum(I), Cout ); END GENERATE MSB; END GENERATE All_Bits END Generate_S ;

14. Unconstrained Ports n Entity Declarations Can Have Ports Defined Using Arrays Without Explicitly Including the Size of the Array n Leads to General Specification of Iterative Circuit Uses Predefined Array Attribute ‘LENGTH

15. Generate e.g., R-C Adder ENTITY RCAdder_N IS PORT ( A, B : IN Bit_Vector ; Cforce : IN Bit ; Sum : OUT Bit_Vector ; Cout : OUT Bit ) ; END RCAdder_N ;

16. Generate e.g., R-C Adder ARCHITECTURE Generate_S OF RCAdder_N IS COMPONENT Full_Adder --defined elsewhere PORT ( A, B, Cin : IN bit ; S, Cout : OUT bit ) ; END COMPONENT Full_Adder ; SIGNAL Int_C : BIT_VECTOR ( (A’LENGTH - 1) DOWNTO 0); Uses Predefined Array Attribute ‘LENGTH

17. Generate e.g., R-C Adder BEGIN --RC Adder All_Bits: FOR I IN (A’LENGTH -1) DOWNTO 0 GENERATE LSB: IF (I = 0) GENERATE BEGIN S0: Full_Adder PORT MAP ( A(I), B(I), Cforce, Sum(I), Int_C(I) ); END GENERATE S0 ; For primary input, not iterative carry Please remember that FOR used here is for structure description. It is different than LOOP used in behavioral descriptions in future

18. Generate e.g., Ripple-Carry- (R-C) Adder Middle_bits: IF ( I 0 ) GENERATE BEGIN SI: Full_Adder PORT MAP ( A(I), B(I), C(I-1), Sum(I), Int_C(I) ); END GENERATE SI ;

19. Generate e.g., R-C Adder MSB: IF ( I = A’LENGTH - 1 ) GENERATE BEGIN SN: Full_Adder PORT MAP ( A(I), B(I), INT_C(I-1), Sum(I), Cout ); END GENERATE MSB; END GENERATE All_Bits END Generate_S ; For primary output, not iterative carry out

20. Problems for students to think about n Generate statement for one dimensional combinational regular structures. n Generate statement for two-dimensional combinational regular structures. n Generate statement for many dimensional circuits. n Generate statement for regular structures of finite state machines and generalized shift registers. n How to describe GAPP processor and similar FPGA structures using “Generate”. n Importance of the “generalized register” model as a prototype of many combinational, sequential, cellular and systolic circuits.

21. Slides used Prof. K. J. Hintz Department of Electrical and Computer Engineering George Mason University