2. Basic Concepts in VHDL Instructors: Fu-Chiung Cheng ( 鄭福炯 ) Associate Professor Computer Science & Engineering Tatung University

3. Outline Timing and Concurrency Object and classes Delay Model Event and Transactions Sequential Placement of Transactions

4. Characteristics of Hardware Components and Carries VHDL == a language for description of hardware VHDL has features for representing characteristics of hardware components and carries: – Timing – Concurrency

5. Timing Transfer of values between components or within a component is done through wires and buses. Transfer values: delays See Fig 4.1 on page 72 – Dotted capacitors represent wire capacitance proportional to the length of the wire segments. – Delay: wire capacitance + gate pull-up or pull-down resistance VHDL need to model the timing property

6. Value transfer through wires. Assignment – value transfer – ignore the timing of transfer a := x; b := x; Assignment – Assignments is scheduled at some time. a <= x AFTER 4*unit_delay; b <= x AFTER 3*unit_delay;

7. Concurrency Functionality of Hardware systems is achieved by concurrently active components communicating through their input and output port. Fig 4.2 on page 73 the system s has three concurrent subcomponents The statements part of an architecture is VHDL concurrent body.

8. Concurrency VHDL concurrent body: – Structural – Behavioral – dataflow VHDL concurrent body: Fig 4.3 on page 74 Statements are executed when events occur Subcomponent is communicating with other subcomponents whose operations may be specified concurrently or sequentially.

9. Sequential body Fig 4.4 on page 75 Process construct ARCHITECTURE sequential... BEGIN... PROCESS... BEGIN... IF THEN ELSE... FOR LOOP... END PROCESS... END ARCHITECTURE

10. PROCESS (clk) VARIABLE count : INTEGER := limit; BEGIN IF (clk = '0' AND clk'EVENT) THEN IF reset = '1' THEN count := 0; ELSE IF count < limit THEN count := count + 1; END IF; END IF; IF count = limit THEN counting <= '0' AFTER td_cnt; ELSE counting <= '1' AFTER td_cnt; END IF;

11. Illustrating timing and concurrency See Fig 4.5 on page 75 – 1 inverter, 2 and, 1 or gates – Inputs: a, b, c (all initial high) – Output: z – Gate delay: 12 ns See Fig 4.6 and 4.7 on page 76 – Signal a (1 == > 0)

12. Gate Reacting Fig 4.6 shows the gate reacting A change in the a input results in domino changes each 12 ns apart No more events occur when output is reached

13. Timing Diagram Fig 4.7 shows the timing diagram A glitch appears on the output Must model hardware to imitate this behavior Requires timing and concurrency in the language

14. Objects and Classes An entity that has a value of a given type is a VHDL object Objects: – Signals: Port signals, signals for interconnecting components – Variables: loop index variables, temporary variables, – Constants: – Files: files

15. Objects and Classes Objects of the signal class: – Represent hardware wires – Have timing associated with them – Values assigned to a signal are placed on the signal driver and will appear on the signal after a specified delay – Can be used in both concurrent and sequential bodies – signal_var <= …. AFTER …. ;

16. Objects and Classes Objects of the variable class: – Are for storage of temporary values – Have no hardware significance – Variables can be used only in sequential bodies – Sequential bodies: processes, procedures, functions – variable_var := …. ;

17. Objects and Classes Objects of the constant class: – Represent constant values of a given type – can be used in both concurrent and sequential bodies

18. Objects and Classes Objects of the file class: – can be used in both concurrent and sequential bodies – Primitives: text input and output

19. Objects and Classes: summaries

20. Signal Assignment Signal assignment can be inertial or transport delay – Inertial delay: signal values less than its some delay are ignore – RC Delay model: See Fig 4.11 on page 80 – transport delay: faithful transport the signal values VHDL delay model: – Assignment with inertial mechanism – Assignment with inertial with reject mechanism – Assignment with transport mechanism

21. VHDL delay model Assignment with inertial mechanism – target1 <= waveform AFTER 5 NS; – A pulse whose width is less than 5 ns is rejected – Delay time = 5ns Assignment with inertial with reject mechanism – target2 <= REJECT 3 NS INERTIAL waveform AFTER 5 NS; – A pulse whose width is less than 3 ns is rejected – Delay time = 5 ns Assignment with transport mechanism – target3 <= TRANSPORT waveform AFTER 5 NS; – Delay time = 5 ns

22. Delay mechanism Demo ENTITY example IS END ENTITY; ARCHITECTURE delay OF example IS SIGNAL waveform : BIT; SIGNAL target1, target2, target3 : BIT; SIGNAL diff12, diff13, diff23 : BIT; BEGIN -- Illustrating inertial delay target1 <= waveform AFTER 5 NS; target2 <= REJECT 3 NS INERTIAL waveform AFTER 5 NS; -- Illustrating transport delay target3 <= TRANSPORT waveform AFTER 5 NS; -- Comparing targets diff12 <= target1 XOR target2; diff13 <= target1 XOR target3; diff23 <= target2 XOR target3;

23. Delay mechanism Demo (cont.) -- Creating waveform waveform <= ‘1’ AFTER 03 NS, ‘0’ AFTER 08 NS, ‘1’ AFTER 14 NS, ‘0’ AFTER 18 NS, ‘1’ AFTER 24 NS, ‘0’ AFTER 27 NS, ‘1’ AFTER 33 NS, ‘0’ AFTER 35 NS, ‘1’ AFTER 41 NS, ‘0’ AFTER 47 NS, ‘1’ AFTER 52 NS, ‘0’ AFTER 58 NS, ‘1’ AFTER 62 NS, ‘0’ AFTER 68 NS, ‘1’ AFTER 71 NS, ‘0’ AFTER 77 NS, ‘1’ AFTER 79 NS, ‘0’ AFTER 85 NS; END delay;

24. VHDL delay mechanism Fig 4.12 on page 82

25. Concurrency ENTITY figure_5_example IS PORT (a, b, c : IN BIT; z : OUT BIT); END figure_5_example; ARCHITECTURE concurrent OF figure_5_example IS SIGNAL w, x, y : BIT; BEGIN w <= NOT a AFTER 12 NS; x <= a AND b AFTER 12 NS; y <= c AND w AFTER 12 NS; z <= x OR y AFTER 12 NS; END concurrent; In architectural body, all signal assignments are concurrent.

26. Concurrency VHDL description for the gate level circuit for the demonstration of timing and concurrency Four concurrent statements model gates of the circuit Events of the RHS cause evaluation and scheduling A scheduled value is a transaction on the driver of the LHS signal

27. Concurrency Multiple signal assignments are simultaneously active The order of signal assignments is not significant A signal may have more than one driver Resolution Function: Resolving a single value from multiple driving values (see Fig 4.14 on page 84)

28. Events and Transactions Event: a signal value is changed by some waveforms. Transaction: (time, value) pair is put on the driver A transaction that expires generates a current driving value

29. Events and Transactions

30. Demo Fig 4.16 on page 86 ARCHITECTURE demo OF example IS SIGNAL a, b, c : BIT := '0'; BEGIN a <= '1' AFTER 15 NS; b <= NOT a AFTER 5 NS; c <= a AFTER 10 NS; END demo;

31. 0 1

33. Delta Delay Ex1 ENTITY timing IS PORT (a, b : IN BIT; z, zbar : BUFFER BIT); END ENTITY; -- ARCHITECTURE delta of timing IS BEGIN z_bar <= NOT z; // delta delay between z_bar and z z <= a AND b AFTER 10 NS; END delta;

34. Delta Delay Ex2 ARCHITECTURE not_properly_timed OF figure_5_example IS SIGNAL w, x, y : BIT := '0'; BEGIN y <= c AND w; w <= NOT a; x <= a AND b; z <= x OR y AFTER 36 NS; END not_properly_timed;

35. Assume at time zero signal a is assigned 0

36. Delta Delay Ex3: ARCHITECTURE concurrent OF timing_demo IS SIGNAL a, b, c : BIT := '0'; BEGIN a <= '1'; b <= NOT a; c <= NOT b; END concurrent;

37. Delta Delay Ex4: inverter chain ARCHITECTURE forever OF oscillating IS SIGNAL x: BIT := ‘0’; SIGNAL y: BIT := ‘1’; BEGIN x <= y; y <= NOT x; END forever;

38. Sequential Placement of Transactions ARCHITECTURE sequential OF sequential_placement IS... BEGIN PROCESS x<= v1 AFTER t1; x<= v2 AFTER t2; WAIT; END PROCESS; END sequential; Two events: (v1, t1) and (v2,t2) When (v2,t2) how about x? 1.Append (v2,t2) to the driver or 2.Overwrite the transaction

39. Sequential Placement of Transactions ARCHITECTURE concurrent OF sequential_placement IS... BEGIN a <= v1, v2 AFTER t2-t1 x <= a AFTER t2; END concurrent; Have the same as effect as the sequential implementation

40. Sequential Placement of Transactions Projected output waveform A new transaction will be compared with all existing transactions It appends, or overrides existing ones

41. Effective Transactions See Fig 4.28 on page 96 For transport signals: – (rule 1) If new transport transaction is before the original transaction then overwrite existing transaction – (rule 2) If new transport transaction is after the original transaction then append the new transaction

42. Rule 1: overwrite existing transaction ARCHITECTURE sequential OF discarding_old IS SIGNAL x : bit := ‘Z’; BEGIN PROCESS BEGIN x <= ‘1’ AFTER 5 NS; x <= TRANSPORT ‘0’ AFTER 3 NS; WAIT; END PROCESS; END sequential;

43. Rule 2: Append new transaction ARCHITECTURE sequential OF saving_all IS SIGNAL x : bit := ‘Z’; BEGIN PROCESS BEGIN x <= ‘1’ AFTER 5 NS; x <= TRANSPORT ‘0’ AFTER 8 NS; WAIT; END PROCESS; END sequential;

44. Effective Transactions (Fig 4.28) For inertial signals: – (rule 3) If new inertial transaction is before the original transaction then overwrite existing transaction – (rule 4) If new inertial transaction is after the original transaction and New Value=existing value then append the new transaction – (rule 5) If new inertial transaction is after the original transaction and New Value(Vnew)!=existing value(Vexisting) and abs(Vnew-Vexisting) > reject value then append the new transaction – (rule 6) If new inertial transaction is after the original transaction and New Value(Vnew)!=existing value(Vexisting) and abs(Vnew-Vexisting) <= reject value then overwrite existing transaction

45. Rule 3: overwrite existing transaction ARCHITECTURE sequential OF overwriting_old IS SIGNAL x : bit := ‘Z’; BEGIN PROCESS BEGIN x <= ‘1’ AFTER 5 NS; x <= ‘0’ AFTER 3 NS; WAIT; END PROCESS; END sequential;

46. Rule 4: Append new transaction ARCHITECTURE sequential OF saving_all IS SIGNAL x : bit := ‘Z’; BEGIN PROCESS BEGIN x <= ‘0’ AFTER 5 NS; x <= ‘0’ AFTER 8 NS; WAIT; END PROCESS; END sequential;

47. Rule 5: Append new transaction ARCHITECTURE sequential OF appending IS SIGNAL x : bit :=’Z’; BEGIN PROCESS BEGIN x <= ‘1’ AFTER 5 NS; x <= REJECT 2 NS INERTIAL ’0’ AFTER 8 NS; WAIT; END PROCESS; END sequential;

48. Rule 6: overwrite existing transaction ARCHITECTURE sequential OF discarding_old IS SIGNAL x : bit := ‘Z’; BEGIN PROCESS BEGIN x <= ‘1’ AFTER 5 NS; x <= REJECT 4 NS INERTIAL ’0’ AFTER 8 NS; WAIT; END PROCESS; END sequential;

49. ENTITY example IS END ENTITY; -- ARCHITECTURE delay OF example IS SIGNAL waveform : BIT; SIGNAL target1, target2, target3 : BIT; BEGIN -- Signal assignments target1 <= waveform AFTER 5 NS; target2 <= REJECT 3 NS INERTIAL waveform AFTER 5 NS; target3 <= TRANSPORT waveform AFTER 5 NS; -- Creating waveform waveform <= '1' AFTER 03 NS, '0' AFTER 08 NS, '1' AFTER 14 NS, '0' AFTER 18 NS, '1' AFTER 24 NS, '0' AFTER 27 NS, '1' AFTER 33 NS, '0' AFTER 35 NS; END delay;

50. Result of sequential placement of transactions

52. ENTITY example IS END ENTITY; -- ARCHITECTURE delay OF example IS SIGNAL a, b : BIT; BEGIN -- Signal assignments a <= '1' AFTER 5 NS, '0' AFTER 10 NS, '1' AFTER 15 NS; b <= '0', a AFTER 3 NS; END delay; 3ns 5ns3ns8ns10ns13ns15ns