CSE - Shiraz University1 Computer Architecture by: Behrooz Nasihatkon Computer Science & Engineering Department Shiraz University

CSE - Shiraz University2 Boolean Algebra Boolean Variables –A = 0, 1 Boolean Functions –F(A, B) = ? F(0,0) = 1 F(0,1) = 1 F(1,0) = 0 F(1,1) = 1 F(A,B,C,D, …)

CSE - Shiraz University3 Boolean Operators (Special Functions) –NOT NOT(0) = 1 NOT(1) = 0 –AND AND(0,0) = 0 AND 0 = 0 AND(0,1) = 0 AND 1 = 0 AND(1,0) = 1 AND 0 = 0 AND(1,1) = 1 AND 1 = 1

CSE - Shiraz University4 Boolean Operators (Special Functions) –OR OR(0,0) = 0 OR 0 = 0 OR(0,1) = 0 OR 1 = 1 OR(1,0) = 1 OR 0 = 1 OR(1,1) = 1 OR 1 = 1 –XOR XOR(0,0) = 0 XOR 0 = 0 XOR(0,1) = 0 XOR 1 = 1 XOR(1,0) = 1 XOR 0 = 1 XOR(1,1) = 1 XOR 1 = 0

CSE - Shiraz University5 Boolean Algebra F(A, B) = ? –F(0,0) = 1 –F(0,1) = 1 –F(1,0) = 0 –F(1,1) = 1 F(A,B) = (~ A) or (A and B)

CSE - Shiraz University6 Logic Gates A B A AND B ANOT A AA B B A XOR BA OR B

CSE - Shiraz University7 Example A B C F(A,B,C) = (~A and B) or C F(A,B,C) = (~A and (B or C)) or ~C A B C

CSE - Shiraz University8 Representing Logical Values +_+_ 5v ~ 0 v 1 ~ +5v

CSE - Shiraz University9 Gates In Circuit +_+_ 5v 0v+5v 0v+5v 0v+5v

CSE - Shiraz University10 Logic Circuits ABCDEFABCDEF f (A,B,C,D,E,F)

CSE - Shiraz University11 Logic Circuits ABCDEFABCDEF f1 (A,B,C,D,E,F) f2 (A,B,C,D,E,F) f3 (A,B,C,D,E,F)

CSE - Shiraz University12 Example 4 bit Adder AB A + B

CSE - Shiraz University13 Example 4 bit Adder / Subtractor A B A + B S 10 A - B

CSE - Shiraz University14 4 to 1 MUX S0 D0 D2 D1 D3 S1 4 bit 2 to 1 MUX S Multiplexer 2 to 1 MUX S D0 D1

CSE - Shiraz University15 ALU simple Arithmetic Logic Unit B A Carry out Carry in S0 S1 S2 B Y A - B110 A + B010 B100 A000 YS0S1S2 A or B111 A and B011 ~ A101 -A-A001 YS0S1S2

CSE - Shiraz University16 Step by Step Operations Adding N numbers (N is Variable) Multiplication (of big numbers) Division Algorithms

CSE - Shiraz University17 Memory Unit Sequential Circuits

CSE - Shiraz University18 Latches Delay Latch D C Q Q = D Hold Data

CSE - Shiraz University19 Flip-Flops Flip Flop D C Q Q  D Clock Where the data has been stored ?

CSE - Shiraz University20 Step by Step Operations D C QD C QD C QD C Q Clock 1 Speed ? Frequncy?

CSE - Shiraz University21 Registers D C QD C QD C QD C D C QD C QD C QD C Clock Parallel Input Parallel Output Load

CSE - Shiraz University22 Registers 8 bit register Clock Parallel Input Parallel Output Load clear inc 8 8

CSE - Shiraz University23 Registers Clock Parallel Input Parallel Output Load shift Serial Input Serial Output left/right Serial Input Serial Output

CSE - Shiraz University24 4 bit Adder 444 C out R1 LD CLK C LD CLK R2 LD CLK clock CLK R3 LD load R3  R2 + R1 C  Carry

CSE - Shiraz University25 Counter/Timer Clock Parallel Output Load Increment 0 1

CSE - Shiraz University26 ALU Example B A Carry in S0 S1 S2 B Y A - B110 A + B010 B100 A000 YS0S1S2 A or B111 A and B011 ~ A101 -A-A001 YS0S1S Carry out Sign overflow zero

CSE - Shiraz University27 Example -A-A001 ~ A101 A and B011 A or B111 A – B110 A + B010 B100 A000 YS0S1S2 ALU A Carry in S2 S1 S0 B Y Carry out Sign overflow zero CF SF OF ZF BL LD ADD AL, BL AL LD MOV AL, BLNEG ALNOT ALAND AL, BL Flag Register 1 LD

CSE - Shiraz University28 Memory Unit x 6 Memory

CSE - Shiraz University29 Read Only Memory Address A0 A1 A2 D0 D5D4D3D2D1 D0 = F(A0, A1, A2) x 6 ROM

CSE - Shiraz University30 Random Access Memory Address 6 Output 6 Input Clock Read Write 8 x 6 RAM 6 Input/Output

CSE - Shiraz University31 General Purpose Computers Programming Basic Instructions

CSE - Shiraz University32 Computer Instructions 16 bit Instruction Operation Code (opcode)

CSE - Shiraz University33 Processor (CPU) 1k x 16 Memory 16 bit Instruction 10 Address 16 Data 10 Address 16 Data opcodeaddress R W RW 10 Address Bus 16 Data Bus R W Control Bus

CSE - Shiraz University34 ADD201 opcodeaddress STO202 opcodeaddress LD200 opcodeaddress 1k x 16 Memory 105: 106: 107: opcodeaddress opcodeaddress opcodeaddress Accumulator (16) Program Counter (10) (Instruction Counter, Instruction Pointer)

35 1k x 16 Memory RW 10 Address Bus Address Register (10) LD 200 opcodeaddress LD Program Counter (10) inc Data Bus 16 Instruction Register (16) LD Data Register (16) LD Accumulator (16) LD ALU S2 S1 S0 AB 10 IR(0-9) S MUX 01 Control Bus Timer Reset Clock Control Unit 105: ADD201 opcodeaddress 106: STO202 opcodeaddress 107:

CSE - Shiraz University36 Von-Newman Architecture Data and Instructions are stored in a common memory Processor –Loop: 1.Fetch Instruction from memory 2.Decode Instruction 3.Execute Instruction –[Fetch Operands from memory] –Execute –[Store results in memory]

CSE - Shiraz University37 Types of Machine Instruction Computation (Arithmetic, Logic, Shift) –ADD, SUB, MUL, AND, OR, XOR, SHL, SHR Data transfer –LOAD, STORE, MOVE, EXCAHNGE, POP, PUSH Program Control –JUMP, conditional JUMP (JZ, JS, …) –COMPARE, TEST –CALL, RETURN

CSE - Shiraz University38 Binary Codes Inserting An instruction –100: –101: –102: Memory Locations Disadvantages of Programming In Machine Language LD200SUB201JNS101ADD1017SUB1018ADD200

CSE - Shiraz University39 Assembly Language Symbolic Labels & Variables Overloading Assembler Each Processor Has an Assembly Language

CSE - Shiraz University40 High-level Programming Languages Types (integer, boolean, string, structures, arrays, etc) Expressions Control Instructions (if-else, while, …) Procedures, Argument passing, …

CSE - Shiraz University41 Compilers/Interpreters Compiler: A program that converts a High-level program code to Machine-Code: –Mapping Variables, Structures and Procedures to Memory Addresses –Writing Codes for Loops, Conditions, Procedure Calls, Argument Passing, etc –Writing Codes for Expression evaluation –Syntax Checking, Type Checking, Errors and Warnings –… Interpreter: A program that Reads Instructions of a High- level programming language and Executes them one by one

CSE - Shiraz University42 Try it yourself ! Write a program in ‘C’ and Compile it to Assembly language:Write a program in ‘C’ and Compile it to Assembly language: >>> gcc –S test.c Read and Modify Assembly Code:Read and Modify Assembly Code: >>> mcedit test.s Convert Assembly code to Machine Code (Executable file) and run it:Convert Assembly code to Machine Code (Executable file) and run it: >>> gcc test.s >>>./a.out

CSE - Shiraz University43 Interrupt Write A Screen Saver Program that displays an animation, Shows clock, and terminates with a key-press or mouse-click: 12:53

CSE - Shiraz University44 Interrupt Loop: –Fetch Instruction –Decode –Execute –If an Interrupt Occurs Save Current Value of Registers Jump to Interrupt Service Routine (ISR) [PC  address of ISR] Hardware Implementation of ‘if’ (i.e. takes no time to check occurring of Interrupt) Address of ISR can be determined by content of a register, Interrupt Vector or it can be fixed.

CSE - Shiraz University45 Types of Interrupt 1.External Interrupt I/O devices, Timers, Alarms, etc 2.Internal Interrupt (Trap) Overflow, Division by zero, Invalid Instruction, Stack Overflow, … 3.Software Interrupt Calling an ISR, Calling System Functions (system calls)

CSE - Shiraz University46 Dynamic Memory Allocation int k; main() { k = fact(7); } int fact(int n) { int m; if (n == 0) return 1; m = fact(n – 1); return m * n; }

CSE - Shiraz University47 Stack k LD 100 JZ 202 DEC : m Return Address n: 6 m Return Address n: 7 xxx Stack Pointer (SP) int k; int fact(int n) { int m; if (n == 0) return 1; m = fact(n – 1); return m * n; } k = fact(7); : Stack Code Data Memory

CSE - Shiraz University48 Limitations of Stack char *upper_case(char *s) { char r[100]; // allocating 100 bytes in stack int i; for (i = 0; s[i] != 0; i++) { if (s[i] >= ‘a’ && s[i] <= ‘z’) r[i] = s[i] – ‘a’ + ‘A’; // Converting to upper-case letter else r[i] = s[i]; } return r; } main() { char *s1 = “Salaam!!”; char *s2 = upper_case(s1); printf(“%s, %s\n”, s1, s2); // Unexpected result! }

CSE - Shiraz University49 Heap char *upper_case(char *s) { char r[100]; // allocating 100 bytes in stack char *r = (char *) malloc(100); // allocating 100 bytes in heap int i; for (i = 0; s[i] != 0; i++) { if (s[i] >= ‘a’ && s[i] <= ‘z’) r[i] = s[i] – ‘a’ + ‘A’; else r[i] = s[i]; } return r; } main() { char *s1 = “Salaam!!”; char *s2 = upper_case(s1); printf(“%s, %s\n”, s1, s2); // prints : Salaam!, SALAAM! free(s2); // return 100 free bytes to heap }

50 Heap k LD 100 JZ 202 DEC : s s2 s1 : Stack Code Data Memory char *upper_case(char *s) { char *r = (char *) malloc(100); int i; for (i = 0; s[i] != 0; i++) { if (s[i]>=‘a’ && s[i]<=‘z’) r[i] = s[i]–‘a’+‘A’; else r[i] = s[i]; } return r; } main() { char *s1 = “Salaam!!”; char *s2 = upper_case(s1); printf(“%s, %s\n”, s1, s2); free(s2); } i r : 1200 ret-address main upper-case : Heap 1200 :

CSE - Shiraz University51 Wait Signal Processor (CPU) 1k x 16 Memory Address Bus 16 Data Bus R W Control Bus RWWait delay Clock 100MHz clock 100ns propagation delay (10ns for each micro-operation)

CSE - Shiraz University52 Processor (CPU) 1k x 16 Memory RWWait delay Clock 100MHz clock (10ns) 64 x 16 Cache (100ns) propagation delay (8ns) propagation delay Cache Memory Data+Address+Control Bus

CSE - Shiraz University53 Cache Memory Associative Mapping Direct Mapping

CSE - Shiraz University54 Virtual Memory : : 1M x 16 Physical Memory 32k x 16 Address Mapping

CSE - Shiraz University55 ? ? ?

CSE - Shiraz University56 Simple ALU -A-A001 ~ A101 A and B011 A or B111 A – B110 A + B010 B100 A000 YS0S1S2