1. Chapter 8: The Very Simple Computer
Computing Machinery
Chapter 8: The Very Simple Computer

2. The Von-Neumann Architecture
The concept of a stored program was part of the design of the Analytical Engine and well understood by Charles Babbage and Augusta Ada King more than 150 years ago.
For some reason, this concept was temporarily lost or forgotten by the middle of the 20th century.
Early electronic computers, such as the ENIAC, kept the logic and arithmetic instructions separate from the data. Some early computers had to be rewired in order to change their programs.
The interpretation of a word in memory as either an instruction or data is determined by its location in memory rather than its pattern of ones and zeros. The content of memory has more than one possible interpretation. For example, the bit pattern,
can represent the integer 1,086,918,618 or an instruction to JUMP to another location (address) in memory, or it could represent an approximation for the numeric value of p.

3. Designing the Very Simple Computer
VSC Instruction
operations code
address
3-bits limits the number of
instructions to 23 = 8
5-bit limits the number of
words to 25 = 32
8-bit instructions will all be direct addressing mode
data type will be integer, twos'-complement
operations will correspond to Post-Turing language
with only 8 instructions, the VSC is the "Ultimate RISC" Computer

4. The Very Simple Computer

5. Program Counter (PC)
Program Counter (PC) - The address of the next instruction that is to be executed is held in a register called the program counter (PC). The value in this register is passed to the memory unit as the address of the instruction to access. During the fetch portion of the fetch-execute cycle, the value in the PC is incremented.

6. Memory Address Register (MAR)
Memory Address Register (MAR) - The memory address register (MAR) of the VSC memory is also a 5-bit register. To read or write a word, we first place the memory address into the MAR and then activate the appropriate control lines (Read/Write, and Memory Enable) to perform the indicated I/O operation.

7. Instruction Register (IR)
Instruction Register (IR) - The VSC is a single-address instruction machine so the instruction register needs room to hold the operations code (op-code) of the instruction to be executed and the address on which the operation is performed. Since the VSC uses 8-bit words, the instruction register (IR) supports a 5-bit address and a 3-bit op-code.

8. Arithmetic Logic Unit (ALU) Latches
ALU Latches (LAT1 and LAT2) - The arithmetic logic unit (ALU) accepts one or two input values. These values are held above the ALU in registers called Latch1 (LAT1) and Latch2 (LAT2). These registers have outputs that are always active since they are directly connected to the ALU and are never used to write to the bus.

9. Accumulator (ACC)
Accumulator (ACC) - The output of the ALU is the result of the execution of some arithmetic or logical operation. This value is held in the accumulator (ACC) until it is moved or otherwise managed by a subsequent instruction. Since the VSC is a single-address instruction CPU, the value in the ACC is transferred to one of the ALU latches during the fetch.

10. The Instruction Set
LDA addr - load the accumulator with the value from memory at address addr
STA addr - store the value in the accumulator into memory at address addr.
ADD addr - add value in memory at address addr to ACC and store in LAT1.
CMP addr - take the 1's complement of the value in memory at address addr
BNN addr - the branch-not-negative statement will set PC = addr if the value in the accumulator is not negative.
SHL addr - shift value in memory at address addr one bit to the left.
SHR addr - shift value in memory at address addr one bit to the right (arithmetic).
HLT - this instruction terminates the fetch-execute cycle.

11. Register Transfer Description

12. The Fetch/Execute Cycle
get the address of the next instruction
load the instruction register with the next instruction
get the address in the current instruction
increment to program counter
move the value in the ALU ACC into LAT2
move the data referred to by the instruction into LAT1
execute the instruction

13. Running the VSC

14. Running the VSC

15. Running the VSC

16. Running the VSC

17. Running the VSC

18. Running the VSC

19. Running the VSC

20. Control Unit Executing OpCodes
LDAen - load ACC enable - moves value in LAT1 into ACC
STAen - store ACC enable - moves value in ACC into MEM[MAR]
ADDen - ADD enable
CMPen - CMP (1's complement) enable - takes the bitwise inverse of LAT1
BNNen - if(ACC7 = 0) then PC = IR<4:0>
SHLen - shift-left enable
SHRen - shift-right enable
HLTen - halts the fetch-execute cycle by setting
Control
Unit IR

21. Control Unit Fetch Operations PCre - PC read enable
PCwe - PC write enable
PCinc - PC increment
MARwe - MAR write enable
IRre - IR read enable
IRwe - IR write enable
LAT1we - LAT1 write enable
LAT2we - LAT2 write enable
ACCwe - ACC write enable (from ALU only)
ACCre - ACC read enable (we read the ACC through the bus)

22. VSC System Clock

23. Fetch-Execute Cycle Timing Diagram

24. Fetch-Execute Control Circuit

25. VSC Instruction Decoder Circuit

26. VSC Memory Unit

27. Arithmetic Logic Unit

28. Bitwise Complement and Shift Operations

29. A 4-Bit ALU

30. VSC Input/Output

31. Programming the VSC addr label instruction addr machine code .
LDA A
ADD B
STO C
HLT
4 A
5 B
6 C

32. Loops in the VSC

33. What is This?