ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE Presenter: Shu-yen Lin Advisor: Prof. An-Yeu Wu 2005/6/6
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 2 Outline Concepts of Xilinx FPGA Xilinx FPGA Architecture Introduction to ISE Code Generator Constraints and Reports Configuration Demo and Lab
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Concepts of Xilinx FPGA
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 4 Electronic Components
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 5 FPGA Benefits Full-Custom ICs Cell-Based ICs Gate ArraysFPGA Speed ●●●●● Integration Density ●●●●● High-Volume Device Cost ●● ●● Low-Volume device Cost ●●● Time to Market ●●● Risk Reduction ●● Future Modification ●● Development Tool ●●●●● Educational Purpose ●●
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 6 Full Xilinx Design Support
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 7 Xilinx Products CPLDs and FPGAs
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Xilinx FPGA Architecture
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 9 The Conceptual CPLD Architecture
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 10 The Conceptual FPGA Architecture Field-programmable Re-programmable In-circuit design verification Rapid prototyping Fast time-to-market No IC-test & NRE cost H/W emulation instead of S/W
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 11 Spatran-2/2E, Virtex / Virtex-E FPGA Architecture (1/6)
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 12 Logic and Routing - the CLB tile Spatran-2/2E, Virtex / Virtex-E FPGA Architecture (2/6)
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 13 Spatran-2/2E, Virtex / Virtex-E FPGA Architecture (3/6) Two slices in each CLB Each slice contains 2 LUT, 2 Register and 2 Carry Logic. Logic and Routing – Simplified CLB Structure
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 14 Spatran-2/2E, Virtex / Virtex-E FPGA Architecture (3/6) Logic and Routing – Look-Up Tables (LUTs) Combinational logic is stored in Look-up Tables (LUTs) in a CLB. Capacity is limited by number of inputs, not complexity. Delay through CLB is constant.
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 15 Spatran-2/2E, Virtex / Virtex-E FPGA Architecture (4/6) System Interface – Select IO TM Supports multiple voltage and signal standards simultaneously Eliminate costly bus transceivers
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 16 System Memory – Distributed RAM, Block RAM and External Memory Spatran-2/2E, Virtex / Virtex-E FPGA Architecture (5/6)
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 17 Spatran-2/2E, Virtex / Virtex-E FPGA Architecture (6/6) System clock management - DLLs Clock Mirror Multiplication 1 DLL for 2x Combine 2 DLL for 4x Division Selectable division values - 1.5, 2, 2.5, 3, 4, 5, 8, or 16 Phase Shift 0, 90, 180, 270
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 18 Spatran-3, VirtexII FPGA Architecture (1/7)
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 19 Spatran-3, VirtexII FPGA Architecture (2/7) Logic and Routing - the CLB tile
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 20 Spatran-3, VirtexII FPGA Architecture (3/7) System Interface – Select IO TM 23 different standards supported !
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 21 Spatran-3, VirtexII FPGA Architecture (4/7) System Memory –External Memory supports DDR memory
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 22 Spatran-3, VirtexII FPGA Architecture (5/7) System clock management – DCMs
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 23 Spatran-3, VirtexII FPGA Architecture (6/7) System clock management – DCMs
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 24 Spatran-3, VirtexII FPGA Architecture (7/7) Embedded multiplexer
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 25 VirtexII Pro FPGA Architecture
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 26 Programmable Logic Evolution
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Introduction to ISE
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 28 ISE Philosophy ISE 6.1i Future Xilinx devices Proactive Timing Closure ECS & HDL Bencher & XST Platform Unix: Solaris 2.7/2.8 PC: Win 2000/XP Service Pack ISE WebPage
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 29 Design Flow in ISE (1/2)
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 30 Design Flow in ISE (2/2)
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 31 Introduction to Projection Navigator (1/4)
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 32 Introduction to Projection Navigator (2/4) Source Windows
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 33 Introduction to Projection Navigator (3/4) Processes for current source
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 34 Introduction to Projection Navigator (4/4) Processes for current source
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 35 Create New Project
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 36 Create New Source
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 37 HDL Source File
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 38 Text Entry
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 39 Language Templates
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 40 Synthesis (1/4) XST
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 41 Synthesis (2/4) XST Flow
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 42 Synthesis (3/4) Synthesis Step
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 43 Synthesis (4/4) RTL view
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 44 Implementation (1/8) Translate - Merge multiple design files into a single netlist Map - Group logical symbols from the netlist (gates) into physical components (CLBs and IOBs) Place & Route - Place components onto the chip, connect them, and extract timing data into reports
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 45 Implementation (2/8)
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 46 Translate Implementation (3/8)
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 47 Map Implementation (4/8)
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 48 Implementation (5/8) Map Property Trim Unconnected Signals If you check this item, the mapping tool will remove the unconnected wire that let the tracing back become hardly. Generate Detailed Map Report If more detailed report is needed, you can check it. (Recommending check it) Use Guide Design File (.ncd) You can refer the last mapping solution so that you maybe get better solution. Use RLOC Constraints Constraints of CLB (default check). Pack I/O Registers/Latches into IOBs If the value chosen Default that pack the register nearby I/O into I/O block. You can also chose only for input or only for output or off.
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 49 Place and Route Implementation (6/8)
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 50 Place and Route Property (1/2) Place & Route Effort Level (Overall) Effort Level means the P&R effect result. Using the Higher get the better solution, but spend more time. Starting Placer Cost Table (0-100) Specify a placement initialization value with which to begin P&R attempts. Each subsequent attempt is assigned an incremental value based on the placement initialization value. Place and Route Mode Quick means without timing constraints; Route Only and Re-entrant Route mean P&R must have been run at last once to use this option. Guide File Include the.ncd file. Implementation (7/8)
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 51 Place and Route Property (2/2) Use Timing Constraints Include the.ucf file. Use Bonded I/Os If it is checked, signals will be connected to I/O pads. Generate Detailed PAR Report Check the value to generate a detailed PAR report. Generate Post-Place & Route Static Timing Report Check the value to generate post-place & route static timing report. Generate Post-Place & Route Simulation Model Check it for generating required simulation files for ModelSim (*.v and *.sdf). Implementation (8/8)
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 52 Download (1/2)
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 53 Download (2/2)
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Code Generator
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 55 What are Cores?
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 56 Benefits of Using Cores
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 57 Invoking the CORE Generator GUI
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 58 Xilinx Code Generator System GUI
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 59 Core Customize Window
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 60 Core Data Sheet
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 61 Core Generator Design Flow
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 62 Link with CodeGen IP (Verilog)
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Constraints and Reports
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 64 Topics Assign Package Pins (PACE) Assigning Pins Create Timing Constraints The PERIOD Constraints The Pad-to-Pad Constraints The OFFSET Constraints The Constraints Editor Read Report
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 65 Constraints GUI (1/2)
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 66 Constraints GUI (2/2)
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 67 Assign Package Pins (1/6) Start PACE Editor
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 68 Assign Package Pins (2/6) PACE Editor GUI
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 69 Assign Package Pins (3/6) Method #1 to assign package pins
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 70 Assign Package Pins (4/6) Method #2 to assign package pins
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 71 Assign Package Pins (5/6) Method #3 to assign package pins
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 72 Assign Package Pins (6/6) Method #4 to assign package pins Use text editor to edit.ucf files NET is port name LOC assign pins to specific location
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 73 The PERIOD Constraint
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 74 The Pad-to-Pad Constraint
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 75 The OFFSET Constraint
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 76 The Constraint Editor (1/3)
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 77 The Constraint Editor (2/3) Enter PERIOD and Pad-to-Pad Constraint
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 78 The Constraint Editor (3/3) Enter OFFSET Constraint
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 79 Read Report (1/12) Create Report Files
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 80 Read Report (2/12)
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 81 Read Report (3/12) Example of MAP Report (1/2)
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 82 Read Report (4/12) Example of MAP Report (2/2)
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 83 Read Report (5/12)
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 84 Read Report (6/12) Example of PAR Report (1/2)
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 85 Read Report (7/12) Example of PAR Report (2/2)
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 86 Read Report (8/12)
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 87 Read Report (9/12) Example of Timing Report (1/4)
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 88 Read Report (10/12) Example of Timing Report (2/4)
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 89 Read Report (11/12) Example of Timing Report (3/4)
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 90 Read Report (11/12) Example of Timing Report (4/4)
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 91 Post-layout Simulation
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Configuration
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 93 What is configuration? Process for loading into the FPGA
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 94 Configuration Mode (1/4)
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 95 Configuration Mode (2/4) Serial Mode
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 96 Configuration Mode (3/4) SelectMAP Mode
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 97 Configuration Mode (4/4) JTAG or Boundary Scan
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 98 IMACT (1/3) Must double clock “Generate Programming File” before programming FPGA
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 99 IMACT (2/3)
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 100 IMACT (3/3)