SAR ATR Challenge Problem Update SLAAC Retreat March 1999 Brian K. Bray Sandia National Laboratories

Joint STARS ‘97 SAR ATR Pipeline Identification Indexer (SLD) Focus of Attention Detection Annotated SAR Image Belief Management (Fusion Executive) MPM CRMMSELPM Joint STARS Advance Workstation (JAWS) ATR Results Display PGA ESAR Image SAR Image T72 Sandia National Labs PowerPC Multicomputer HPSCAlpha WSMercury *Not Joint STARS imagery Hardware Used DARPA EHPC Hardware

Flight System: —early two-level multiprocessor ATR System Hardware Evolution For: 1 Mpixel/sec with 6 target configurations (targets in-the-clear scenario) Baseline 1996 System: —Systolic, SIMD, very early two-level multiprocessor/DSP Current two-level multiprocessor configuration implements algorithms with better performance and significantly lower power, size, and weight versus baseline implementation Power (W)Volume (ft 3 ) Sandia National Labs 1999 TCTA System: —maturing two-level multiprocessor W 160 Weight (lbs.) lbs ft (5 VME chassis) (2 VME chassis) W- ft 3 -lbs 10,407, ,204 28,000 Power, Volume, Weight Product (W- ft 3 -lbs.) 26X reduction 371X reduction

Surveillance Challenge Problem - SAR / ATR 40,000 sqnm / 1 ft. Resolution CurrentChallengeSystem ParameterScale Factor SAR Area Coverage Rate (sqnm / ft Res.) 40, X (FOA, * * Corresponds to a data rate of 40 Megapixels / sec Level / Difficulty of CC&D HighLow100X (Indexer) 10X (Ident.) Number of Target Classes X (Indexer, Ident.) Indexer, Ident.)

SLAAC’s Competition Quad PowerPC G3 boards (now - end ‘99) –CSPI 2741 w/1MB L2$, 64MB/node –Mercury w/1MB L2$, 128MB/node Quad PowerPC G4 boards (‘00 - ?) PowerPC G5 boards (?)

ATR Latency Tests Sandia National Labs

MPI Bandwidth Benchmark Sandia National Labs

MPI Latency Benchmark Sandia National Labs

Deployable Reference Platform (DRP) Myrinet Diagram Host Workstation Myricom FPGA Motorola SBC & CSPI 2741 Sandia National Labs

Myricom FPGA Board Implementing SLD It works, but –implementation is out-of-date with current algorithm –some calculation errors truncation instead of rounding in an integer divide? Reliability is poor –Power-up and LANai/FPGA load reliability is poor poor reset circuitry? –Flashing LEDs for status was extremely helpful Need to work on extra buffering in the host node so the FPGA worker nodes always have work Coprocessor model for low-level control of FPGA accelerators (instead of remote LANai method of Myricom FPGA board) is still the way to go

Near-Term Performance Goal for SLAAC 100X over ‘96 baseline system by using latest EHPC and ACS technology –2 Mpixels/sec for 6 partially obscured target types –~20X there with COTS two-level multicomputers (EHPC) –need ~5X more from ACS need ~10X from ACS on FOA and Indexing some performance loss from –not all operations are implemented in ACS –overhead in control of ACS

Proposal for what to do for Fall SAR ATR Lab Demo? Use embedded SLAAC2 boards –SLD? –hosted on CSPI 2X41S carrier boards –shows embedded capability Use latest generation COTS PCI FPGA board –FOA, CDI? –use Annapolis Micro Systems Wildstar? –Add two embedded PC chassis to DRP to host the PCI FPGA cards with Myrinet PCI card which OS? (Myricom MCP drivers for Linux and Solaris x86, what about Wildstar board?) doesn’t show 6U VME insertion but will show ACS performance gains