By Praveen Venkataramani Techniques for Test Power Reduction in Leading Edge IP Using Cadence Encounter Test -ATPG: By Praveen Venkataramani

Objective To reduce dynamic power during test in scan based designs To obtain test vector sequences with minimum switching and pattern count without any loss in test coverage

Overview[1] Test power consumption is 3x – 5x the functional power Can cause false failures due to IR drop as a result of high switching in scan test Shift Power Cause High toggle during shift Fix Reduction in overall toggle activity- Use fill techniques Capture Power Toggle Activity due to circuit response Using clock gating technique – Functional clock is gated from areas that are not required for functional operation at that time Test power consumption is 3x-5x the functional power consumption. The culprits are scan shift and capture. 3

Experimental Setup 45nm Cortex A8 ARM IP Functional clock - 600 MHz Flop Count – 130,000 Clock Domains – 5 (only 1 Domain with 97%of flops is used for the experiments) Launch on Capture Length of Scan chains FULSCAN – 8 chains Average chain length : 17281 flip flops Longest chain length : 17344 flip flops Compression- 904 chains Average chain length: 152 flip flops Longest chain length: 155 flip flops Tool Used – Cadence Encounter Test (Cadence ET) Default setting Compaction Effort – Ultimate Fill – Random fill All Flops switch at capture Compaction of several test responses – Signature

Vector Compression

Vector Compression Multiple chips are tested on an automated test equipment (ATE). Number of available scan channels(ports) from ATE is small compared to the ports in the CUT Available storage in ATE for test vectors Need for decompress and compress the test vectors used for test Decompress the data during testing and compress during storage (minimum memory used)

Compression Structure[2]

Compression Modes Broadcast Using XOR gates One channel from the ATE fanouts (“broadcasts”)to multiple scan chains Using XOR gates The vector on the scan chain is a function of the input and the XOR gates

Broadcast Decompression/Spreader Broadcast spreader XOR Compression Masking logic ATE Scan Chain 1 ATE Scan Chan 2 Scan Chain 3 Scan channels Scan Chain n-2 Scan Chain n-1 Compressed Output Scan Chain n CUT contains 904 Scan chains with 152 Flip flops on average Longest chain contains 157 flip flops Mask Enable pins Scan Enable Pin Internal Clock generator Tester clock pin

XOR Spreader and Decompressor XOR Compression Masking logic ATE ATE Scan Chain 1 Scan Chan 2 Scan channels Scan Chain 3 Scan Chain n-2 Compressed Output Scan Chain n-1 Scan Chain n Mask Enable pins Scan Enable Pin Internal Clock generator Tester clock pin

Channel Masking

Channel Masking X X X X X X X X X X From the Scan chains To ATE Circuit may produce “X”s during testing, “X”s maybe due to open/ high impedance nodes, race conditions X’s Corrupt the compressed output, Mask “X” from reaching the output

Channel Masking- Types [3] Types Wide 0, Wide1, Wide 2 CUT uses Wide2 Mask logic Contains 2 Mask registers R0 and R1 Mask register is pre-loaded before scan out. Sets the ‘X’ to value in the Mask bit Prevents output data from corruption Some good values could be masked

Scan Shift Toggle Reduction

Fill Techniques in Cadence ET[4] Toggle activity during scan test is high Reduce toggle activity using fill techniques Random Repeat ‘0’ or ‘1’ Method 1: explicitly specify the fill technique Method 2: specify the allowed percentage toggle activity Method 3: Dual fill, combination of repeat and random fill. In Dual fill the ATPG switches from one fill type to the next after a specified test coverage. It doesn’t reduce the peak toggle % but reduces the toggle activity on an average over the entire test sequence length.

Filling of “Don’t-care” Bits- Fullscan Mode (Cadence ET®)

Filling of “Don’t-care” Bits- Fullscan Mode (Cadence ET®)

Average Toggle Activity during scan shift in Fullscan Mode

Fault Analysis-Fullscan Mode Dynamic Fault Analysis Report Fill Type Total Faults Test Coverage % Test Sequence Random 4937768 88.51 6536 Zero 88.41 13217 Repeat 88.47 8187 100 50 88.52 6649 25 88.53 6797

Summary of Percentage Reduction in Peak Toggle Activity Fill Type Total Faults Full Scan Broad Cast XOR Compression Test sequence increase % Reduction in Toggle Maxscan_50 5270394 1.02 42.17 41.17 0.97 0.64 Maxscan_25 1.04 50.13 0.89 51.30 1.00 9.53 repeat 1.25 79.72 53.94 9.54 one 1.36 77.01 54.60 1.03 9.72 zero 2.02 87.62 1.28 53.23 1.35 14.98

Average Power Analysis using Synopsys PrimeTime-PX [5]- Fullscan mode Pattern Sequential Switching Power (in mW) Random Repeat Initial % Reduction Final 3 0.0281 0.0166 40.9 0.0167 40.5 4 0.0293 0.0176 39.9 0.0174 5 0.0286 38.4 39.5

IR Drop Analysis

IR Drop IR Drop occurs due to interconnect resistance between VDD to cell or macro VDD domains vdd_mpu and vddlsw_mpu result in maximum IR drops For proper operation of the circuit, the minimum allowable voltage must not be below15% of the reference VDD, in this case 1.08 V.

Max Dynamic IR Drop Gradient map-Random Fill vector Shows the minimum VDD-VSS over the timing window for each instance, i.e. the maximum Voltage drop for each instance.

Max Dynamic IR Drop Gradient map- Repeat Fill Vector

Switching Histogram- Random Fill Vector This shows the number of instances switching over the simulation time. Used to check how many instances are switching simultaneously and verify whether simultaneous switching is the reason for the dynamic voltage drop.

Switching Histogram- Repeat Fill Vector There is about 60% reduction in the number of instances switched using repeat fill vectors

Scan Capture Toggle Reduction Reason for toggle during scan capture What is clock gating? Results from Cadence ET

Capture Toggle Capture toggle occurs due to the circuit response Difficult to control through scan in vectors Option- to mask the flip flops that don’t need to be toggled Use clock gates available in the circuit

Clock gate Information of the CUT Test Clock Domain (MHz) Total Number of Flip flops Number of flip flops not controllable with clock gates Number of flip flops controllable with clock gates Percentage flip flops controllable Lowest Max capture setting available 200 539 4 535 99.26 1 600 127825 100 150 64727 2 375 57.96 749 6 743 99.2 3859 2117 1742 45.14

Toggle Activity during Capture- Fullscan Compaction Effort Max Permitted Toggle% during capture Max Toggle activity % observed during capture Ultimate none Specified 41.68 40 41.61 30 20 10 None 41.66 41.51

Future work Pattern Generation and analysis for reduction in toggle activity during scan capture. Use the generated vector on ATE to test the CUT

References Ravi, S. , "Power-aware test: Challenges and solutions," Test Conference, 2007. ITC 2007. IEEE International , vol., no., pp.1-10, 21-26 Oct. 2007 doi: 10.1109/TEST.2007.4437660 http://www.cadence.com/rl/Resources/conference_papers/3.7Presentation.pdf Vivek Chickermane, Brian Foutz, and Brion Keller. 2004. Channel Masking Synthesis for Efficient On-Chip Test Compression. In Proceedings of the International Test Conference on International Test Conference (ITC '04). IEEE Computer Society, Washington, DC, USA, 452-461. Encounter Test Low Power user guide Synopsys PrimeTime PX user guide Apache Redhawk user guide “The Power of RTL Clock-gating”, by Mitch Dale, http://chipdesignmag.com/display.php?articleId=915