ECE 3110: Introduction to Digital Systems Chapter 5 Combinational Logic Design Practices X-OR gates and Parity circuits Comparators Adders, subtractors, ALUs

2 Previous class Building blocks Encoders/priority encoders Three state buffers/inverters Multiplexers/demultiplexers

3 Exclusive OR and Exclusive NOR Gates XOR : XNOR : Truth Table : XOR X Y XOR XNOR XOR X Y F X Y F

4 XOR and XNOR Symbols Equivalent Symbols of XOR gate Equivalent Symbols of XNOR gate Any 2 signals (inputs or outputs) may be complemented without changing the resulting logic function

5 SSI XOR and XNOR 74x86 : 4 XOR gates 74x266: 4 XNOR gates with “open collector” or “open drain” output

6 XOR Application: Parity Circuit Odd Parity Circuit : The output is 1 if odd number of inputs are 1 Even Parity Circuit : The output is 1 if even number of inputs are 1 Example : 4 bit Parity Circuit : Daisy-Chain Structure Tree structure Input : 1101 Odd Parity output : 1 Even Parity output: 0 I0 I1 I2 I3 ODD EVEN I0 I1 I2 I3 ODD EVEN

7 MSI Parity Circuit : 74x280

8 Parity-Checking Application:memory

9 Comparators Compares Two binary words and indicate if they are equal Magnitude Comparators : A Comparator OUTPUT B A Comparator A=B B A>B A<B

10 Equality Comparators 1-bit comparator 4-bit comparator EQ_L

11 General structure of an iterative combinational circuit

12 Multibit Iterative Comparator

13 MSI Comparator : 74x85 4 bit comparator 3 outputs : A=B, A B 3 Cascading inputs Functional Output equations : (A>B OUT)= (A>B)+(A=B).(A>B IN) (A<B OUT)= (A<B)+(A=B).(A<B IN) (A=B OUT)= (A=B).(A=B IN) Cascading inputs initial values : (A=B IN) =1 (A>B IN) =0 (A<B IN) =0 B0 A1 B1 A2 B2 A3 A0 B3 74x85 A<BIN A=BIN A>BIN A<BOUT A=B OUT A>BOUT

14 8 bit Comparator B0 A1 B1 A2 B2 A3 A0 B3 74x85 A<BIN A=BIN A>BIN A<BOUT A=B OUT A>BOUT B0 A1 B1 A2 B2 A3 A0 B3 74x85 A<BIN A=BIN A>BIN A<BOUT A=B OUT A>BOUT B0 A1 B1 A2 B2 A3 A0 B3 B4 A5 B5 A6 B6 A7 A4 B7 +5V A<B A=B A>B Most Significant bitsLeast Significant bits

15 8-bit Magnitude Comparator

16 Other conditions

ECE311 Ch5 17 Adders/Subtractors Half Adder Full Adder Ripple Adder Full Subtractor Ripple Subtractor Adder/Subtractor Circuit

ECE311 Ch5 18 Half Adder: adds two 1-bit operands Truth table : X Y HS=(X+Y) CO Y X H S CO

19 Full Adders: provide for carries between bit positions Basic building block is “full adder” 1-bit-wide adder, produces sum and carry outputs Truth table: XYCinSCout S is 1 if an odd number of inputs are 1. COUT is 1 if two or more of the inputs are 1. Recall: Table 2-3, pp32

20 Full-adder circuit

21 Ripple adder Speed limited by carry chain Faster adders eliminate or limit carry chain 2-level AND-OR logic ==> 2 n product terms 3 or 4 levels of logic, carry lookahead

22 74x283 4-bit adder Uses carry lookahead internally

23 16-bit group- ripple adder

24 Subtraction Subtraction is the same as addition of the two’s complement. The two’s complement is the bit-by-bit complement plus 1. Therefore, X – Y = X + Y’ + 1

25 Full subtractor = full adder, almost X,Y are n-bit unsigned binary numbers Addition : S = X + Y Subtraction : D = X - Y = X + (-Y) = = X+ (Two’s Complement of Y) = X+ (One’s Complement of Y) + 1 = X+ Y’+ 1

ECE311 Ch5 26 Using Adder as a Subtractor Ripple Adder can be used as a subtractor by inverting Y and setting the initial carry ( CIN ) to 1

ECE311 Ch5 27 MSI Arithmetic Logic Units (ALU ) ALU performs Aithmetic and Logical Functions - A, B : 4 bits inputs - S3,S2,S1,S0 : Function select - M=0 : Arithmetic operations +=Plus, - = Minus M=1 : Logical operations : += OR,. =AND Example : Inputs Functions S3 S2 S1 S0 M=0 M= F= A-1+CIN F=A’ F= A-B-1+CIN F=A XOR B’ F= A+B+CIN F=A XOR B F=(A OR B)+ CIN F=A+B F= A+A+CIN F= F=A+CIN F=A S1 S2 S3 F1 F2 M CIN A0 S0 F0 B0 74x181 F3 COUT A1 B1 A2 B2 A3 B3 A=B P G

ECE311 Ch5 28 Chapter Summary Documentation Standards: - Gate symbols, Signals Active Levels, Bubble to Bubble Logic - Block diagram, Schematic Diagram, Timing Diagram. Combinational Logic design Structures: 1-Decoders : Binary Decoders, Cascading decoders, Implementing Logic Functions, Seven-Segment Decoders (HW5.18). 2-Encoders : Binary Encoder, Priority Encoder, Cascading Encoders, Encoder applications. 3-Three State Buffers : SSI buffers, MSI Octal Buffer, Octal Three-state Transceiver

29 Chapter Summary 4- Multiplexers : MUX operation, Single/Multiple outputs MUX, Expanding MUXs 5- Demultiplexers : MUX/DMUX operation, Using Decoders as Demultiplexers. 6- XOR and XNOR Gates: Logic Symbols, Equivalent Symbols, Parity Circuits using XOR gate, Parity Circuit application ( memory unit checking ) 7- Comparators : Parallel Comparators, Iterative Comparators, Cascading Comparators 8-Adders : Half Adder, Full Adder, Ripple Adder, Subtractor, Ripple Adder / Subtractor Unit,Group-Ripple Adder 9- Arithmetic Logic Units

30 Next… HW #9 Combinational circuits Design examples Reading Wakerly Chapter 6