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1 EE365 Three-state Outputs Encoders Multiplexers XOR gates.

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Presentation on theme: "1 EE365 Three-state Outputs Encoders Multiplexers XOR gates."— Presentation transcript:

1 1 EE365 Three-state Outputs Encoders Multiplexers XOR gates

2 2 Three-state buffers Output = LOW, HIGH, or Hi-Z. Can tie multiple outputs together, if at most one at a time is driven.

3 3 Different flavors

4 4

5 5 Timing considerations

6 6 Three-state drivers

7 7 Driver application

8 8 Three-state transceiver

9 9 Transceiver application

10 10 Encoders vs. Decoders DecoderEncoder

11 11 Binary encoders

12 12 Need priority in most applications

13 13 8-input priority encoder

14 14 Priority-encoder logic equations

15 15 74x148 8-input priority encoder –Active-low I/O –Enable Input –“Got Something” –Enable Output

16 16 74x148 circuit

17 17 74x148 Truth Table

18 18 Cascading priority encoders 32-input priority encoder

19 19 Constant expressions

20 20 Outputs

21 21 Alternative formulation WHEN is very natural for priority function

22 22 Multiplexers

23 23 74x151 8-input multiplexer

24 24 74x151 truth table

25 25 CMOS transmission gates 2-input multiplexer

26 26 Other multiplexer varieties 2-input, 4-bit-wide –74x157 4-input, 2-bit-wide –74x153

27 27 Barrel shifter design example n data inputs, n data outputs Control inputs specify number of positions to rotate or shift data inputs Example: n = 16 –DIN[15:0], DOUT[15:0], S[3:0] (shift amount) Many possible solutions, all based on multiplexers

28 28 16 16-to-1 muxes 16-to-1 mux = 2 x 74x151 8-to-1 mux + NAND gate

29 29 4 16-bit 2-to-1 muxes 16-bit 2-to-1 mux = 4 x 74x157 4-bit 2-to-1 mux

30 30 Properties of different approaches

31 31 2-input XOR gates Like an OR gate, but excludes the case where both inputs are 1. XNOR: complement of XOR

32 32 XOR and XNOR symbols

33 33 Gate-level XOR circuits No direct realization with just a few transistors.

34 34 CMOS XOR with transmission gates IF B==1 THEN Z = !A; ELSE Z = A;

35 35 Multi-input XOR Sum modulo 2 Parity computation Used to generate and check parity bits in computer systems. –Detects any single-bit error

36 36 Parity tree Faster with balanced tree structure

37 37 Next time Comparators Adders Multipliers Read-only memories (ROMs)


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