Ch 5. Logic Design with MSI Components

Csci 2021 Srping02 2 VHDL The U.S. Department of Defense (DoD) supported the development of VHDL (VHSIC hardware description language) as part of the VHSIC (very high-speed IC) program in the early 1980s. The companies in the VHSIC program found they needed something more than schematic entry to describe large ASICs, and proposed the creation of a hardware description language. VHDL was then handed over to the Institute of Electrical and Electronics Engineers (IEEE) in order to develop and approve the IEEE Standard As part of its standardization process the DoD has specified the use of VHDL as the documentation, simulation, and verification medium for ASICs (MIL-STD-454). Partly for this reason VHDL has gained rapid acceptance, initially for description and documentation, and then for design entry, simulation, and synthesis as well.1 The first revision of the 1076 standard was approved in References to the VHDL Language Reference Manual (LRM) in this chapter--[VHDL 87LRM2.1, 93LRM2.2] for example--point to the 1987 and 1993 versions of the LRM [IEEE, and ]. The prefixes 87 and 93 are omitted if the references are the same in both editions. Technically (known as VHDL-87) is now obsolete and replaced by (known as VHDL-93). Except for code that is marked 'VHDL-93 only' the examples in this chapter can be analyzed (the VHDL word for "compiled") and simulated using both VHDL- 87 and VHDL-93 systems. 93LRM2.2

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7 Logic Gates and Symbols a b F a b F a F F = a b F = a + bF = ! a AndOr Not ABF ABF AF 01 10

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Csci 2021 Srping02 11 Logic Equation Representation: Sum-of-Products (SOP) SOP form: A collection of ANDed variables are Ored together. Example: ABF F = !A!B + AB Also called XNOR

Csci 2021 Srping02 12 Example of SOP Example: A three-input majority function The function is true when more than half of its inputs are true F =? ABCF

Csci 2021 Srping02 13 Example of SOP Example: A three-input majority function The function is true when more than half of its inputs are true F = !ABC+A!BC+AB!C+ABC ABCF

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Csci 2021 Srping02 15 Digital Components High level digital designs are usually made using collections of logic gates. Such collection of gates are referred as components. Multiplexer and Decoder are commonly used digital components. Levels of integration SSI (Small Scale Integration) components per chip MSI (Medium Scale Integration) 100-1,000 components per chip LSI (Large Scale Integration) ,000 components per chip VLSI (Very Large Scale Integration) – Higher ULSI (Ultra Large Scale Integration) – Higher, higher!

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Csci 2021 Srping02 18 Example: using MUX for Majority

Csci 2021 Srping02 19 An 8-bit multiplexer entity Mux8 is generic (TPD : TIME := 1 ns); port (A, B : in BIT_VECTOR (7 downto 0); Sel : in BIT := '0'; Y : out BIT_VECTOR (7 downto 0)); end; architecture Behave of Mux8 is Begin Y <= A after TPD when Sel = '1' else B after TPD; end; Eight 2:1 MUXs with single select input. Timing: TPD (input to Y) = 1 ns

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Csci 2021 Srping02 22 Example: Using Decoder for Majority

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Csci 2021 Srping02 27 Carry-InABSumCarry-out Sum = A’BC’ + AB’C’ + A’B’C + ABC Carry-out = ABC’ + A’BC + AB’C + ABC

Csci 2021 Srping02 28 A full adder Entity Full_Adder is generic (TS : TIME := 0.11 ns; TC : TIME := 0.1 ns); port (X, Y, Cin: in BIT; Cout, Sum: out BIT); end Full_Adder; architecture Behave of Full_Adder is begin Sum <= X xor Y xor Cin after TS; Cout <= (X and Y) or (X and Cin) or (Y and Cin) after TC; end; Timing: TS (Input to Sum) = ns TC (Input to Cout) = 0.1 ns

Csci 2021 Srping02 29 An 8-bit ripple-carry adder entity Adder8 is port (A, B: in BIT_VECTOR(7 downto 0); Cin: in BIT; Cout: out BIT; Sum: out BIT_VECTOR(7 downto 0)); end Adder8; architecture Structure of Adder8 is component Full_Adder port (X, Y, Cin: in BIT; Cout, Sum: out BIT); end component; signal C: BIT_VECTOR(7 downto 0); begin Stages: for i in 7 downto 0 generate LowBit: if i = 0 generate FA:Full_Adder port map (A(0),B(0),Cin,C(0),Sum(0)); end generate; OtherBits: if i /= 0 generate FA:Full_Adder port map (A(i),B(i),C(i-1),C(i),Sum(i)); end generate; Cout <= C(7); end;

Csci 2021 Srping02 30 The single input line into each AND gate represents 6 input lines The single input line into each OR gate represents 8 lines Darkened circles are placed at crosspoints to indicate connections are made

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Csci 2021 Srping02 34 When A,B,C all changed from 0 to 1, there will Be a glitch.

Csci 2021 Srping02 35 Flip-Flop A Flip-flop is an arrangement of logic gates that maintains a stable output even after the inputs are made inactive. A flip flop can be used to store a single bit of information. A S-R flip flop holds a single bit of information and serve as an elementary memory cell. In order to achieve synchronization in a controlled fashion, a clock signal is provided. Every state-dependent circuit synchronizes itself by accepting inputs only at discrete times.

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Csci 2021 Srping02 44 Truth Table for Mod-4 Counter RESETS1S0S1/S0Q1/Q0 0000/1 0011/0 0101/1 0110/ Note that S1/S0 are identical to Q1/Q0

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Csci 2021 Srping02 49 Finite State Machine 4X5 PLA Q D S0 Q D S1 X1 X0 Z2 Z1 Z0 CLK

Csci 2021 Srping02 50 Truth Table for Vending Machine S1S0X1X0S1S0Z0Z1Z

Csci 2021 Srping02 51 Example Assume our vending machine takes only nickels and dimes. The machine vends items for 15 cents. What is the state transition diagram?

Csci 2021 Srping02 52 Example Assume our vending machine takes only nickels and dimes. The machine vends items for 15 cents. What is the state transition diagram? A 0 cent B 5 cent C 10 cent N/00 N/10 D/00 D/10 D/11 N/D: Nickel or Dime 0/1: dispense or not 0/1: return nickel or not