We think you have liked this presentation. If you wish to download it, please recommend it to your friends in any social system. Share buttons are a little bit lower. Thank you!
Presentation is loading. Please wait.
supports HTML5 video
Published byEsmond Horn
Modified over 4 years ago
Boolean Algebra and Digital LogicChapter 3 Boolean Algebra and Digital Logic Linda Null, Julia Lobur
Figure 03.UN01: "I've always loved that word, Boolean."Claude Shannon
Table 03.T01: Truth Table for AND-
Table 03.T02: Truth Table for OR-
Table 03.T03: Truth Table for NOT-
Table 03.T04: The Truth Table for F(x,y,z) = x + y′z-
Table 03.T05: Basic Identities of Boolean Algebra-
Table 03.T06: Truth Table for the AND Form of DeMorgan's Law-
Table 03.T07: Truth Table Representation for a Function and Its Complement-
Table 03.T08: Truth Table Representation for the Majority Function-
Figure 03.F01: The Three Basic Gates-
Figure 03.F02: a) The Truth Table for XOR b) The Logic Symbol for XOR-
Figure 03.F03: Truth Table and Logic Symbols for NAND-
Figure 03.F04: Truth Table and Logic Symbols for NOR-
Figure 03.F05: Three Circuits Constructed Using Only NAND Gates-
Figure 03.F06: A Three-Input OR Gate Representing x + y + z
Figure 03.F07: A Three-Input AND Gate Representing x yz
Figure 03.F08: AND Gate with Two Inputs and Two Outputs-
Figure 03.F09: Logic Diagram for F(x, y, z) = x + y'z-
Figure 03.UN02: Line drawing showing a circuit.-
Figure 03.F10: Simple SSI Integrated Circuit-
Figure 03.UN08: Line drawing showing a function that evaluates to one AND gate using x and y as input. -
Table 03.T09: Truth Table for a Half-Adder
Figure 03.F11: Logic Diagram for a Half-Adder
Figure 03.F12: a) Truth Table for a Full-Adder b) Logic Diagram for a Full-Adder
Figure 03.F13: Logic Diagram for a Ripple-Carry Adder
Figure 03.F14: a) A Look Inside a Decoder b) A Decoder Symbol-
Figure 03.F15: a) A Look Inside a Multiplexer b) A Multiplexer Symbol-
Table 03.T10: Parity Generator-
Table 03.T11: Parity Checker-
Figure 03.F16: 4-Bit Shifter -
Figure 03.F17: A Simple Two-Bit ALU
Figure 03.F18: A Clock Signal Indicating Discrete Instances of Time-
Figure 03.F19: Example of Simple Feedback-
Figure 03.F20: SR Flip-Flop Logic Diagram
Figure 03.F21: a) SR Flip-Flop b) Clocked SR Flip-Flop c) Characteristic Table for the SR Flip-Flop d) Timing Diagram for the SR Flip-Flop (assuming initial state of Q is 0) -
Table 03.T12: Truth Table for SR Flip-Flop
Figure 03.F22: a) JK Flip-Flop b) JK Characteristic Table c) JK Flip-Flop as a Modified SR Flip-Flop d) Timing Diagram for JK Flip-Flop (assuming initial state of Q is 0) -
Figure 03.F23: a) D Flip-Flop b) D Flip-Flop Characteristic Table c) D Flip-Flop as a Modified SR Flip-Flop d) Timing Diagram for D Flip-Flop -
Figure 03.F24: JK Flip-Flop Represented as a Moore Machine
Figure 03.F25: Simplified Moore Machine for the JK Flip-Flop
Figure 03.F26: JK Flip-Flop Represented as a Mealy Machine
Figure 03.F27: a) Block Diagram for Moore Machines b) Block Diagram for Mealy Machines-
Figure 03.F28: Components of an Algorithmic State Machine-
Figure 03.F29: Algorithmic State Machine for a Microwave Oven-
Figure 03.UN02: Finite State Machine for Accepting a Variable Name-
Figure 03.F30: a) 4-Bit Register b) Block Diagram for a 4-Bit Register
Figure 03.F31: 4-Bit Synchronous Counter Using JK Flip-Flops
Figure 03.F32: 4 x 3 Memory -
Figure 03.F33: Convolutional Encoder for PRML-
Figure 03.F34: Stepping Through Four Clock Cycles of a Convolutional Encoder.-
Table 03.T13: Characteristic Table for the Convolutional Encoder in Figure 3.33-
Figure 03.F35: Mealy Machine for the Convolutional Encoder in Figure 3.33-
Figure 03.F36: Mealy Machine for a Convolutional Decoder-
Figure 03.F37: Trellis Diagram Illustrating State Transitions for the Sequence 00 10 11 11-
Figure 03.F38: Trellis Diagram Illustrating Hamming Errors for the Sequence 10 10 11 11-
Figure 03.AP01: Minterms for Two Variables-
Figure 03.AP02: Minterms for Three Variables-
Figure 03.AP03: Kmap for F(x,y) = x + y-
Figure 03.AP04: Groups Contain Only 1s-
Figure 03.AP05: Groups Cannot Be Diagonal-
Figure 03.AP06: Groups Must Be Powers of 2-
Figure 03.AP07: Groups Must Be as Large as Possible-
Figure 03.AP08: Minterms and Kmap Format for Three Variables-
Figure 03.AP09: Minterms and Kmap Format for Four Variables-
Figure 03.UN10: Illustration of a Kmap with 3 circled groups.-
Assignments The submission has to be by the end of this week Write your full name and the group number on the answer sheet.
ECE 3110: Introduction to Digital Systems Chapter 6 Combinational Logic Design Practices XOR, Parity Circuits, Comparators.
التصميم المنطقي Second Course
Sequential Circuits1 DIGITAL LOGIC DESIGN by Dr. Fenghui Yao Tennessee State University Department of Computer Science Nashville, TN.
Digital Electronics Chapter 5 Synchronous Sequential Logic.
Circuits require memory to store intermediate data
Nonlinear & Neural Networks LAB. CHAPTER 13 Analysis of Clocked Sequential Circuit 13.1 A Sequential Parity Checker 13.2 Analysis by Signal Tracing 13.3.
ECE 331 – Digital System Design Introduction to and Analysis of Sequential Logic Circuits (Lecture #20) The slides included herein were taken from the.
Chapter 4 Gates and Circuits.
CHAPTER 3 Digital Logic Structures
Give qualifications of instructors: DAP
Chapter 8 -- Analysis and Synthesis of Synchronous Sequential Circuits.
Combinational Logic1 DIGITAL LOGIC DESIGN by Dr. Fenghui Yao Tennessee State University Department of Computer Science Nashville, TN.
ECE 301 – Digital Electronics Introduction to Sequential Logic Circuits (aka. Finite State Machines) and FSM Analysis (Lecture #17)
ECE 331 – Digital Systems Design Introduction to Sequential Logic Circuits (aka. Finite State Machines) and FSM Analysis (Lecture #19)
Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved The Digital Logic Level.
Boolean Algebra and Digital Logic
Chapter 3 Boolean Algebra and Digital Logic. 2 Chapter 3 Objectives Understand the relationship between Boolean logic and digital computer circuits. Learn.
CS 105 Digital Logic Design
Sequential Circuits Chapter 4 S. Dandamudi To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, S.
© 2019 SlidePlayer.com Inc. All rights reserved.