Chapter 3 Interconnect: Wire Models Boonchuay Supmonchai Integrated Design Application Research (IDAR) Laboratory June 22, revised July 1,2006

B.Supmonchai Digital ICs Interconnect: Wire Models 2 Outlines  Interconnects at first glance  Wire Capacitances  Wire Resistances  Wiring Models  Wire Inductance

B.Supmonchai Digital ICs Interconnect: Wire Models 3 Physical Interconnect: The Wire Schematics TransmittersReceivers

B.Supmonchai Digital ICs Interconnect: Wire Models 4 Interconnect (Wire) Models All-inclusive model (R, L, and C present) Capacitance-only

B.Supmonchai Digital ICs Interconnect: Wire Models 5 Modern Interconnect   State-of-the-art processes offer multiple layers of aluminum or copper, and at least one layer of polysilicon   Even the n+ and p+ diffusion layers can be used for wiring purposes.

B.Supmonchai Digital ICs Interconnect: Wire Models 6 Interconnect Impact on Chip

B.Supmonchai Digital ICs Interconnect: Wire Models 7 5 metal layers Ti/Al - Cu/Ti/TiN Polysilicon dielectric Example: Intel 0.25 micron Process

B.Supmonchai Digital ICs Interconnect: Wire Models 8 Source: Intel Global Interconnect S Global = S = S Die S Local = S Technology Local Interconnect Nature of Interconnect

B.Supmonchai Digital ICs Interconnect: Wire Models 9 Interconnect Parasitics  Effects of Interconnect parasitics  reduce reliability  affect performance and power consumption  Classes of parasitics  Capacitive  Resistive  Inductive

B.Supmonchai Digital ICs Interconnect: Wire Models 10 Parasitic Simplifications  Inductive  Inductive effects can be ignored if substantial enough Al  The resistance of the wire is substantial enough (as is the case for long Al wires with small cross section)  The rise and fall times of the applied signals are slow enough low resistivity  When the wire is short, or the cross-section is large, or the interconnect material has low resistivity, a capacitance only model can be used

B.Supmonchai Digital ICs Interconnect: Wire Models 11 Parasitics Simplifications (Cont.) interwire  When the separation between neighboring wires is large, or when the wires run together for only a short distance, interwire capacitance can be ignored and all the parasitic capacitance can be modeled as capacitance to ground

B.Supmonchai Digital ICs Interconnect: Wire Models 12 Example: A Simple Wire Model Fanout

B.Supmonchai Digital ICs Interconnect: Wire Models 13 Outlines  Interconnects at first glance  Wire Capacitances  Wire Resistances  Wiring Models  Wire Inductance

B.Supmonchai Digital ICs Interconnect: Wire Models 14 Wiring Capacitance length width fan-out  The wiring capacitance depends upon the length and width of the connecting wires and is a function of the fan-out from the driving gate and the number of fan-out gates.  Wiring capacitance is growing in importance with the scaling of technology.  There are 3 components in wiring capacitance  Parallel Plate Capacitance  Fringing Capacitance  Interwire Capacitance

B.Supmonchai Digital ICs Interconnect: Wire Models 15 Capacitance: The Parallel Plate Model L W H Current Flow Substrate Dielectric tDtDtDtD Electric Field  di = Dielectric permittivity constant (SiO 2 = 3.9)

B.Supmonchai Digital ICs Interconnect: Wire Models 16 (Relative) Permittivity of Some Materials Material  di Free space1 Teflon AF2.1 Aromatic thermosets (SiLK)2.6 – 2.8 Polyimides (organic)3.1 – 3.4 Fluorosilicate glass (FSG)3.2 – 4.0 Silicon dioxide 3.9 – 4.5 Glass epoxy (PCBs)5 Silicon nitride7.5 Alumina (package)9.5 Silicon11.7

B.Supmonchai Digital ICs Interconnect: Wire Models 17 Fringing Capacitance WL H HW-H/2 First Approximate Model W-H/2 H Second Approximate Model + (per length Capacitance)

B.Supmonchai Digital ICs Interconnect: Wire Models 18 Fringing versus Parallel Plate For SiO 2 with relative permittivity = 3.9  W/H  For larger values of W/H (smaller values of H/t di ) the total capacitance approaches the parallel-plate model.  1 pF/cm  Total capacitance levels off to a constant value of approx. 1 pF/cm for line widths smaller than the insulator thickness (i.e., is no longer a function of the width)

B.Supmonchai Digital ICs Interconnect: Wire Models 19 Interwire Capacitance fringingparallel Interwire Interwire capacitance is responsible for Cross-Talk

B.Supmonchai Digital ICs Interconnect: Wire Models 20 Impact of Interwire Capacitance For SiO 2 with relative permittivity = 3.9 W < 1.75H  When W < 1.75H interwire capacitance starts to dominate  Interwire capacitance is more pronounced for wires in the higher interconnect layers (further from the substrate) L 2  Wire delay nearly proportional to L 2

B.Supmonchai Digital ICs Interconnect: Wire Models 21 Wiring Capacitances (0.25 µm CMOS) FieldActivePolyAl1Al2Al3Al4 Poly Al Al Al Al Al PolyAl1Al2Al3Al4Al5 Interwire Cap per unit wire length in aF/  m for minimally-spaced wires PP in aF/  m 2 fringe in aF/  m PP in aF/  m 2 fringe in aF/  m

B.Supmonchai Digital ICs Interconnect: Wire Models 22 Examples of Wire Capacitances Al1  Consider a wire of 10 cm long and 1 micron wide routed in Al1 (e.g., clock line) (over field) then  C pp 3 pF  C pp = (0.1 x 10 6 micron 2 ) x 30 aF/micron 2 = 3 pF  C fringe 8 pF  C fringe = 2 x (0.1 x 10 6 micron) x 40 aF/micron = 8 pF  Now, if a second wire is routed alongside the first wire with minimum separation  C interwire 9.5 pF  C interwire = (0.1 x 10 6 micron) x 95 aF/micron = 9.5 pF Al4  The same wire, if it were routed in Al4 (over field),  C pp = 0.65 pFC fringe = 2.8 pFC interwire = 8.5 pF  C pp = 0.65 pF, C fringe = 2.8 pF, C interwire = 8.5 pF

B.Supmonchai Digital ICs Interconnect: Wire Models 23 Dealing with Capacitances Low Capacitance (low-k)  Use of Low Capacitance (low-k) dielectrics (insulators) such as polymide or even air instead of SiO 2 thermally and mechanically  Family of materials that are low-k dielectrics must be suitable thermally and mechanically  Must also be compatible with (copper) interconnect  Copper  Copper interconnect allows wires to be thinner without increasing their resistance, thereby decreasing interwire capacitance

B.Supmonchai Digital ICs Interconnect: Wire Models 24 Dealing with Capacitances (Cont.) SOI  Use SOI (silicon on insulator) to reduce junction capacitance  Rules of thumb!  Never run wires in diffusion  Use poly only for short runs  Shorter wires – lower R and C  Thinner wires – lower C but higher R

B.Supmonchai Digital ICs Interconnect: Wire Models 25 Outlines  Interconnects at first glance  Wire Capacitances  Wire Resistances  Wiring Models  Wire Inductance

B.Supmonchai Digital ICs Interconnect: Wire Models 26 Wire Resistance L W H R =  L H W  L L L L A = R1R1 R2R2 = Sheet Resistance R  Resistance of a square conductor is independent of its absolute size

B.Supmonchai Digital ICs Interconnect: Wire Models 27 Interconnect Resistance Material  (  -m) Silver (Ag)1.6 x Copper (Cu)1.7 x Gold (Au)2.2 x Aluminum (Al)2.7 x Tungsten (W)5.5 x Material Sheet Res. (  /  ) n, p well diffusion1000 to 1500 n+, p+ diffusion50 to 150 silicide n+, p+ diffusion with silicide 3 to 5 polysilicon150 to 200 silicide polysilicon with silicide 4 to 5 Aluminum 0.05 to 0.1 Resistivity of commonly used conductor (at 20 C) Sheet Resistance for a typical 0.25 micron CMOS process Aluminum used due to low cost and compatibility with fab processAluminum used due to low cost and compatibility with fab process Top of the line processes (e.g., IBM) are now increasingly using Copper as the conductor of choiceTop of the line processes (e.g., IBM) are now increasingly using Copper as the conductor of choice

B.Supmonchai Digital ICs Interconnect: Wire Models 28 HW  =  (  /(  f  )) f where f is frequency  = 4  x H/m  = 2.6  m for Al at 1 GHz Skin Effect  At high frequency, currents tend to flow primarily on the surface of a conductor with the current density falling off exponentially with depth into the wire 2(W+H)  so the overall cross section is ~ 2(W+H)  Example: H = 10 and W = 20, at 1 GHz effective cross section area is not 200 but 2(10+20)2.6 = 156

B.Supmonchai Digital ICs Interconnect: Wire Models 29 Skin Effect (Cont.) f s where the skin depth is equal to half the largest dimension of the wire.  The onset of skin effect is at f s  where the skin depth is equal to half the largest dimension of the wire. f s = 4  / (   (max(W, H)) 2 )  where  is the permeability of the surrounding dielectric f s  Below f s, the whole wire is conducting current  Skin effect increases resistance of the wire due to the decreased effective cross section area.

B.Supmonchai Digital ICs Interconnect: Wire Models 30 Skin Effect for Different W’s Frequency (Hz) % Increase in Resistance W = 1 um W = 10 um W = 20 um 1E81E91E10 for H =.70 um A 30% increase in resistance is observed for 20  m Al wires at 1 GHz (versus only a 1% increase for 1  m wires)

B.Supmonchai Digital ICs Interconnect: Wire Models 31 Dealing with Resistance  Selective Technology Scaling WH  Scale W while holding H constant  Use Better Interconnect Materials  Lower resistivity materials like copper  Silicides  Silicides (WSi 2, TiSi 2, PtSi 2 and TaSi) 8-10 times  Conductivity is 8-10 times better than poly alone  More Interconnect Layers  Reduce average wire-length  Reduce average wire-length (but beware of extra contact!)

B.Supmonchai Digital ICs Interconnect: Wire Models 32 Polycide Gate MOSFET n + n + SiO 2 PolySiliconSilicide p A silicide is a compound material formed using silicon and a refractory metal to create a highly conductive material that can withstand high- temperature process steps without melting. A silicide is a compound material formed using silicon and a refractory metal (W, Ti 2, Pt 2 and Ta) to create a highly conductive material that can withstand high- temperature process steps without melting.

B.Supmonchai Digital ICs Interconnect: Wire Models 33 Outlines  Interconnects at first glance  Wire Capacitances  Wire Resistances  Wiring Models  Wire Inductance

B.Supmonchai Digital ICs Interconnect: Wire Models 34 Electrical Wire Models delay, power dissipation, reliability  Parasitics of the interconnect have an impact on the behavior of the circuit: delay, power dissipation, and reliability  To study these effects, electrical wire models are introduced to simulate the real behavior of the wire as a function of its parameters.  From simple to complex models are:  Ideal Wire Model  Lumped C Model  Lumped RC Model  Distributed RC Model

B.Supmonchai Digital ICs Interconnect: Wire Models 35 Ideal Wire Model no attached parameters or parasitics  Wires are treated as simple lines with no attached parameters or parasitics equi-potential  Same voltage is present at every segment of the wire at every point in time - at equi-potential  Voltage change at one end propagates immediately to the other ends, no matter how far, without delay.  Only holds for very short wires, i.e., interconnects between very nearest neighbor gates  Small circuit components: gates

B.Supmonchai Digital ICs Interconnect: Wire Models 36 Lumped Model  Different fractions (distributed parasitics) can be lumped into a single circuit element, if dominant  Only a single parasitic component (R, C, or L) is dominant small  The interaction between the components is small focus  Only one aspect of the circuit behavior is the focus  Advantage  Advantage: Effects of parasitics can be described by an ordinary differential equation  Distributed Model requires Partial Differential Eq.

B.Supmonchai Digital ICs Interconnect: Wire Models 37 Lumped C Model  When the resistive component is small and the switching frequency is low to medium, only capacitive component of the wire can be considered and lumped into a single C Still equipotential!  Simple yet effective; only introduces the loading effect of the capacitor onto the driving gate

B.Supmonchai Digital ICs Interconnect: Wire Models 38 Lumped RC model  Total wire resistance is lumped into a single R and total capacitance into a single C CwCwCwCw RwRwRwRw V in V out R driver driverwire  Good for short wires; pessimistic and inaccurate for long wires

B.Supmonchai Digital ICs Interconnect: Wire Models 39 (r,c,L) VNVN V in rLrL VNVN rLrLrLrLrLrLrLrL cLcLcLcLcLcLcLcLcLcL Distributed RC model L  Circuit parasitics are distributed along the length, L, of the wire  crper unit length  c and r are the capacitance and resistance per unit length Diffusion Equation (N  )(N  )(N  )(N  )

B.Supmonchai Digital ICs Interconnect: Wire Models 40 RC Tree Characteristics What is a RC Tree? A RC Network is a Tree if …  A unique resistive path exists between the source node and any node of the network  Single input (source) node, s  All capacitors are between a node and GND  No resistive loops

B.Supmonchai Digital ICs Interconnect: Wire Models 41 RC Tree Elmore Delay intractable  Solving for Delay time at any points in the tree is intractable.  Exact Analyses involve solving differential equations of very high degree.  Every Capacitor added raises the degree of the differential equations by one.  Elmore Delay Calculation is a reasonable approximation to the exact solution.  Beware of the Tree assumption! pessimistic  Once again, good for short wires and give pessimistic results.

B.Supmonchai Digital ICs Interconnect: Wire Models 42 RC Tree Elmore Delay (Cont.)  Path resistance  Path resistance  sum of the resistances on the path from the input node to node i R ii =  R j  (R j  [path(s  i)])  Shared path resistance  Shared path resistance  resistance shared along the paths from the input node to nodes i and k R ik =  R j  (R j  [path(s  i)  path(s  k)]) iRC  Elmore Delay at node i in an RC tree is given by first-order time constant of the network

B.Supmonchai Digital ICs Interconnect: Wire Models 43 Example: Elmore Delay Calculation  Find the Delay (after input dropped) at terminal 4.

B.Supmonchai Digital ICs Interconnect: Wire Models 44 RC Chain Elmore Delay C1C1C1C1 C2C2C2C2 C i-1 CiCiCiCi CNCNCNCN R1R1R1R1 R2R2R2R2 R i-1 RiRiRiRi RNRNRNRN V in VNVNVNVN 12i-1iN  1 = C 1 R 1  1 = C 1 R 1  2 = C 1 R 1 + C 2 (R 1 +R 2 )  2 = C 1 R 1 + C 2 (R 1 +R 2 )  i = C 1 R 1 + C 2 (R 1 +R 2 )+…+C i (R 1 +R 2 +…+R i )  i = C 1 R 1 + C 2 (R 1 +R 2 )+…+C i (R 1 +R 2 +…+R i ) Elmore delay Elmore delay equation If all R i are equal and all C i are equal then  i = N(N+1)RC/2

B.Supmonchai Digital ICs Interconnect: Wire Models 45 A Simple Distributed RC Wire Model LN L/N  An RC wire of length L can be modeled by N segments of equal length L/N rc,  Given r and c, the wire resistance and wire capacitance per unit length r L/Nc L/N  The resistance and capacitance of each segment are given by r L/N and c L/N  From the RC chain Elmore delay,

B.Supmonchai Digital ICs Interconnect: Wire Models 46 Distributed RC Model Approximation N  For large number of segments N In terms of distributed parameter  Observation: quadraticL  Delay of a wire is a quadratic function of its length, L half  The delay is only half of that predicted by the lumped RC model

B.Supmonchai Digital ICs Interconnect: Wire Models 47 Step Responses of RC Wire Models 01 L = 1 VoVoVoVo ViViViVi Needs to solve a set of partial differential equations Parameter Voltage Range Lumped RC Distributed RC Prop. Delay - t p 0  50% 0  50% 0.69 RC 0.38 RC Delay Const. -  0  63% 0  63% RC 0.5 RC Rise time - t r (Fall time - t f ) 10%  90% 2.2 RC 0.9 RC 0  90% 0  90% 2.3 RC 1.0 RC

B.Supmonchai Digital ICs Interconnect: Wire Models 48 Other Distributed Lumped Models Distributed π Model Distributed T Model Accuracy-+

B.Supmonchai Digital ICs Interconnect: Wire Models 49 Step Response Examples  Consider a Al1 wire 10 cm long and 1  m wide lumped C  Using a lumped C only model with a source resistance (R Driver ) of 10 k  and a total lumped capacitance (C lumped ) of 11 pF t p 76 nst p = 0.69 x 10 k  x 11pF = 76 ns t r 242 nst r = 2.2 x 10 k  x 11pF = 242 ns distributed RC  Using a distributed RC model with c = 110 aF/  m and r =  /  m t p 31.4 nst p = 0.38 x (0.075  /  m) x (110 aF/  m) x (10 5  m) 2 = 31.4 ns t r nst r = 0.9 x (0.075  /  m) x (110 aF/  m) x (10 5  m) 2 = ns Poly: t rPoly: t r = 0.38 x (150  /  m) x (88+2  54 aF/  m) x (10 5  m)  s = 112  s Al5: t r 4.2 nsAl5: t r = 0.38 x (  /  m) x (5.2+2  12 aF/  m) x (10 5  m) 2 = 4.2 ns

B.Supmonchai Digital ICs Interconnect: Wire Models 50 Propagation Delay Total Delay Putting It All Together (R w C w )/2 ≥ R s C w L ≥ 2R s /r w  The delay introduced by wire resistance becomes dominant when (R w C w )/2 ≥ R s C w (when L ≥ 2R s /r w ) L crit 2.67 cm  For an R s = 1 kΩ driving a 1 µm-wide Al1 wire, L crit is 2.67 cm

B.Supmonchai Digital ICs Interconnect: Wire Models 51 © MJIrwin, PSU, 2000 Design Rules of Thumb  rc t pRC >> t p,gate  rc delays should only be considered when t pRC >> t p,gate of the driving gate L crit >>  t p,gate /0.38rc L crit  Actual L crit depends upon the size of the driving gate and the interconnect material  rc RC  rc delays should only be considered when the rise (fall) time at the line input is smaller than RC, the rise (fall) time of the line t rise < RC  when not met, the change in the signal is slower than the propagation delay of the wire

B.Supmonchai Digital ICs Interconnect: Wire Models 52 Outlines  Interconnects at first glance  Wire Capacitances  Wire Resistances  Wiring Models  Wire Inductance

B.Supmonchai Digital ICs Interconnect: Wire Models 53 V in V out llllrrrr cccc ggg g Inductance comparable  When the rise and fall times of the signal become comparable to the time of flight of the signal waveform across the line, then the inductance of the wire starts to dominate the delay behavior  The condition holds only when the switching speed is sufficiently fast and the quality of the interconnect material is high enough that the resistance of the wire is kept within bounds.

B.Supmonchai Digital ICs Interconnect: Wire Models 54 The Transmission Line Effects wave rc  Signal propagates over the wire as a wave (rather than diffusing as in rc only models) capacitiveinductive  Signal propagates by alternately transferring energy from capacitive to inductive modes ringing  reduces speed  It causes ringing – when wave is reflected back on itself  reduces speed  To avoid wave reflection of signal we must terminate the wire correctly (a matched termination, avoid open and short circuit terminations)

B.Supmonchai Digital ICs Interconnect: Wire Models 55 More Design Rules of Thumb  Transmission line effects should be considered when the rise or fall time of the input signal (t r, t f ) is smaller than the time-of-flight of the transmission line (t flight ) t r (t f ) < 2.5 t flight = 2.5 L/v v where v is the velocity (speed) of propagation within the medium (Al) t r < 150 ps  For on-chip wires with a max. length of 1 cm, we only worry about transmission line effects when t r < 150 ps

B.Supmonchai Digital ICs Interconnect: Wire Models 56 More Design Rules of Thumb (Cont.)  Transmission line effects should be considered only when the total resistance of the wire is limited R < 5 Z 0 = 5 (V/I) Z 0 where Z 0 is the characteristic impedance of the wire  Z 0  Z 0 is a function of the dielectric medium and the geometry of the conducting wire and isolator (it is independent of the length of the wire and the frequency of its signal).  Typical values of characteristic impedances of wires in semiconductor circuits is from 10 to 200 ohms

B.Supmonchai Digital ICs Interconnect: Wire Models 57 Intel P856.5 Al, 0.25  m  M2  M3  M4  M1  M5 Scale: 2,160 nm  M2  M3  M4  M1  M5  M6 Intel P858 Al, 0.18  m IBM CMOS-8S CU, 0.18  m  M1  M6  M7  M2  M3  M4  M5 From MPR, 2000 Wire Spacing Comparisons Closer, C increased Copper, C ~ C P858

B.Supmonchai Digital ICs Interconnect: Wire Models 58 From MPR, 2000 Comparison of Wire Delays Relative speed of a 200-micron M3 wire for four metal/dielectric systems. All three copper wires were the same thickness and the aluminum wire was scaled to the same sheet resistance.