1. © Digital Integrated Circuits 2nd Inverter Impact of Interconnect  Interconnection  Fundamental limitation of Digital Technology at all scales  Classes of parasitics: –Capacitive –Resistive –Inductive (Impact usually package/board level)

2. © Digital Integrated Circuits 2nd Inverter Interconnect Impact on Chip

3. © Digital Integrated Circuits 2nd Inverter Nature of Interconnect Global Interconnect S Local = S Technology S Global = S Die Source: Intel

4. © Digital Integrated Circuits 2nd Inverter INTERCONNECT Capacitance

5. © Digital Integrated Circuits 2nd Inverter Capacitance of Wire Interconnect

6. © Digital Integrated Circuits 2nd Inverter Capacitance: The Parallel Plate Model

7. © Digital Integrated Circuits 2nd Inverter Permittivity

8. © Digital Integrated Circuits 2nd Inverter Fringing Capacitance

9. © Digital Integrated Circuits 2nd Inverter Fringing versus Parallel Plate

10. © Digital Integrated Circuits 2nd Inverter Interwire Capacitance

11. © Digital Integrated Circuits 2nd Inverter Impact of Interwire Capacitance

12. © Digital Integrated Circuits 2nd Inverter Wiring Capacitances (0.5  m CMOS) LayerN+P+PolyPoly2M1M2M3 Sub42073087--321610 aF/  m 2 Ndif2450 aF/  m 2 Pdif2360 aF/  m 2 Poly86057169 aF/  m 2 Poly252 aF/  m 2 M13113 aF/  m 2 M232 aF/  m 2 Sub(fr)310250765939 aF/  m Poly(fr)613828 aF/  m M1(fr)5133 aF/  m M2(fr)52 aF/  m

13. © Digital Integrated Circuits 2nd Inverter INTERCONNECT Resistance

14. © Digital Integrated Circuits 2nd Inverter Wire Resistance

15. © Digital Integrated Circuits 2nd Inverter Interconnect Resistance

16. © Digital Integrated Circuits 2nd Inverter Polycide Gate MOSFET n + n + SiO 2 PolySilicon Silicide p Silicides: WSi 2, TiSi 2, PtSi 2 and TaSi Conductivity: 8-10 times better than Poly

17. © Digital Integrated Circuits 2nd Inverter Sheet Resistance

18. © Digital Integrated Circuits 2nd Inverter Example: Intel 0.25 micron Process 5 metal layers Ti/Al - Cu/Ti/TiN Polysilicon dielectric

19. © Digital Integrated Circuits 2nd Inverter InterconnectModeling

20. © Digital Integrated Circuits 2nd Inverter The Lumped Model

21. © Digital Integrated Circuits 2nd Inverter The Lumped RC-Model The Elmore Delay

22. © Digital Integrated Circuits 2nd Inverter The Ellmore Delay RC Chain

23. © Digital Integrated Circuits 2nd Inverter Wire Model Assume: Wire modeled by N equal-length segments For large values of N:

24. © Digital Integrated Circuits 2nd Inverter The Distributed RC-line

25. © Digital Integrated Circuits 2nd Inverter Step-response of RC wire as a function of time and space

26. © Digital Integrated Circuits 2nd Inverter RC-Models

27. © Digital Integrated Circuits 2nd Inverter Driving an RC-line

28. © Digital Integrated Circuits 2nd Inverter Design Rules of Thumb  rc delays should only be considered when t pRC >> t pgate of the driving gate Lcrit >>  t pgate /0.38rc  rc delays should only be considered when the rise (fall) time at the line input is smaller than RC, the rise (fall) time of the line t rise < RC  when not met, the change in the signal is slower than the propagation delay of the wire © MJIrwin, PSU, 2000

29. © Digital Integrated Circuits 2nd Inverter Homework 4 1. For the AMIS 0.5um technology, create an equivalent RC/Elmore SUE model using the Mosis parametric test results (amis05.txt from web site). This model should include the effective gate capacitance, source and drain parasitic junction capacitances and equivalent resistance for NMOS and PMOS, L=0.5um as a function of W in um. Use this model to estimate the sizes of the transistors in the ring oscillator test for the standard and wide case from the given performance data. (Do this carefully, this is a useful model!!) 2. Rabaey Chap. 4 on-line problems: 1, 4, 7, 12