FlowMap: An Optimal Technology Mapping Algorithm for Delay Optimisation in Lookup- Table Based FPGA Designs 04/06/2016 1 Presented by Qiwei Jin.

Slides:

Advertisements

Similar presentations

Enhanced matrix multiplication algorithm for FPGA Tamás Herendi, S. Roland Major UDT2012.

Advertisements

VHDL - I 1 Digital Systems. 2 «The designer’s guide to VHDL» Peter J. Andersen Morgan Kaufman Publisher Bring laptop with installed Xilinx.

ECE Synthesis & Verification - Lecture 2 1 ECE 667 Spring 2011 ECE 667 Spring 2011 Synthesis and Verification of Digital Circuits High-Level (Architectural)

ECE 667 Synthesis & Verificatioin - FPGA Mapping 1 ECE 667 Synthesis and Verification of Digital Systems Technology Mapping for FPGAs D.Chen, J.Cong, DAOMap.

FPGA Technology Mapping Dr. Philip Brisk Department of Computer Science and Engineering University of California, Riverside CS 223.

University Of Vaasa Telecommunications Engineering Automation Seminar Signal Generator By Tibebu Sime 13 th December 2011.

EELE 367 – Logic Design Module 2 – Modern Digital Design Flow Agenda 1.History of Digital Design Approach 2.HDLs 3.Design Abstraction 4.Modern Design Steps.

Zheming CSCE715.  A wireless sensor network (WSN) ◦ Spatially distributed sensors to monitor physical or environmental conditions, and to cooperatively.

ECE 667 Synthesis and Verification of Digital Systems

➢ Performing Technology Mapping and Optimization by DAG Covering: A Review of Traditional Approaches Evriklis Kounalakis.

Lecture 26: Reconfigurable Computing May 11, 2004 ECE 669 Parallel Computer Architecture Reconfigurable Computing.

1 DAOmap: A Depth-optimal Area Optimization Mapping Algorithm for FPGA Designs Deming Chen, Jacon Cong ICCAD 2004 Presented by: Wei Chen.

ENGIN112 L38: Programmable Logic December 5, 2003 ENGIN 112 Intro to Electrical and Computer Engineering Lecture 38 Programmable Logic.

Caltech CS184a Fall DeHon1 CS184a: Computer Architecture (Structures and Organization) Day10: October 25, 2000 Computing Elements 2: Cascades, ALUs,

Exploiting Symmetry in SAT-Based Boolean Matching for Heterogeneous FPGA Technology Mapping Yu Hu 1, Victor Shih 2, Rupak Majumdar 2 and Lei He 1 1 Electrical.

EDA (CS286.5b) Day 3 Clustering (LUT Map and Delay) N.B. no lecture Thursday.

CS294-6 Reconfigurable Computing Day 15 October 13, 1998 LUT Mapping.

EDA (CS286.5b) Day 19 Covering and Retiming. “Final” Like Assignment #1 –longer –more breadth –focus since assignment #2 –…but ideas are cummulative –open.

Penn ESE535 Spring DeHon 1 ESE535: Electronic Design Automation Day 3: January 27, 2008 Clustering (LUT Mapping, Delay) Please work preclass example.

Bachelor of Applied Science Thesis Defense An Analysis of Network-on-Chip Implementations on Field Programmable Gate Arrays Kevan Thompson Computer Engineering.

Penn ESE535 Spring DeHon 1 ESE535: Electronic Design Automation Day 17: March 30, 2009 Clustering (LUT Mapping, Delay)

Optimality Study of Logic Synthesis for LUT-Based FPGAs Jason Cong and Kirill Minkovich VLSI CAD Lab Computer Science Department University of California,

FPGA Technology Mapping Algorithms

FPGA Technology Mapping. 2 Technology mapping:  Implements the optimized nodes of the Boolean network to the target device library.  For FPGA, library.

CS 151 Digital Systems Design Lecture 38 Programmable Logic.

Digital System Design EEE344 Lecture 1 INTRODUCTION TO THE COURSE

Dr. Konstantinos Tatas ACOE201 – Computer Architecture I – Laboratory Exercises Background and Introduction.

EKT303/4 PRINCIPLES OF PRINCIPLES OF COMPUTER ARCHITECTURE (PoCA)

Library of Efficient Data types and Algorithms (LEDA)

Section I Introduction to Xilinx

Computer Science, Software Engineering & Robotics Workshop, FGCU, April 27-28, 2012 FPGA: Field Programmable Gate Arrays Vincent Giannone Mentor: Dr. Janusz.

1 - ECpE 583 (Reconfigurable Computing): Placing Applications onto FPGAs, Part II Iowa State University (Ames) ECpE 583 Reconfigurable Computing Lecture.

Shashi Kumar 1 Logic Synthesis: Course Introduction Shashi Kumar Embedded System Group Department of Electronics and Computer Engineering Jönköping Univ.

Introduction CSE 1310 – Introduction to Computers and Programming Vassilis Athitsos University of Texas at Arlington 1.

POWER-DRIVEN MAPPING K-LUT-BASED FPGA CIRCUITS I. Bucur, N. Cupcea, C. Stefanescu, A. Surpateanu Computer Science and Engineering Department, University.

FPGA Switch Block Design Dr. Philip Brisk Department of Computer Science and Engineering University of California, Riverside CS 223.

Ch.9 CPLD/FPGA Design TAIST ICTES Program VLSI Design Methodology Hiroaki Kunieda Tokyo Institute of Technology.

1 H ardware D escription L anguages Modeling Digital Systems.

CSE 494: Electronic Design Automation Lecture 2 VLSI Design, Physical Design Automation, Design Styles.

05/04/06 1 Integrating Logic Synthesis, Tech mapping and Retiming Presented by Atchuthan Perinkulam Based on the above paper by A. Mishchenko et al, UCAL.

Introduction to FPGA Created & Presented By Ali Masoudi For Advanced Digital Communication Lab (ADC-Lab) At Isfahan University Of technology (IUT) Department.

Penn ESE535 Spring DeHon 1 ESE535: Electronic Design Automation Day 24: April 18, 2011 Covering and Retiming.

Lecture 10: Logic Emulation October 8, 2013 ECE 636 Reconfigurable Computing Lecture 13 Logic Emulation.

DAOmap: A Depth-optimal Area Optimization Mapping Algorithm for FPGA Designs Deming Chen and Jason Cong Computer Science Department University of California,

Introduction to FPGAs Dr. Philip Brisk Department of Computer Science and Engineering University of California, Riverside CS 223.

Lecture 13: Logic Emulation October 25, 2004 ECE 697F Reconfigurable Computing Lecture 13 Logic Emulation.

1 - CPRE 583 (Reconfigurable Computing): VHDL to FPGA: A Tool Flow Overview Iowa State University (Ames) CPRE 583 Reconfigurable Computing Lecture 5: 9/7/2011.

EKT303/4 PRINCIPLES OF PRINCIPLES OF COMPUTER ARCHITECTURE (PoCA)

1 A Min-Cost Flow Based Detailed Router for FPGAs Seokjin Lee *, Yongseok Cheon *, D. F. Wong + * The University of Texas at Austin + University of Illinois.

Evaluating and Improving an OpenMP-based Circuit Design Tool Tim Beatty, Dr. Ken Kent, Dr. Eric Aubanel Faculty of Computer Science University of New Brunswick.

CALTECH CS137 Winter DeHon CS137: Electronic Design Automation Day 3: January 12, 2004 Clustering (LUT Mapping, Delay)

Lecture 6: Mapping to Embedded Memory and PLAs September 27, 2004 ECE 697F Reconfigurable Computing Lecture 6 Mapping to Embedded Memory and PLAs.

CALTECH CS137 Spring DeHon 1 CS137: Electronic Design Automation Day 5: April 12, 2004 Covering and Retiming.

ELEE 4303 Digital II Introduction to Verilog. ELEE 4303 Digital II Learning Objectives Get familiar with background of HDLs Basic concepts of Verilog.

An Improved “Soft” eFPGA Design and Implementation Strategy

FPGA CAD 10-MAR-2003.

Introduction CSE 1310 – Introduction to Computers and Programming Vassilis Athitsos University of Texas at Arlington 1.

DAOmap: A Depth-optimal Area Optimization Mapping Algorithm for FPGA Designs Deming Chen, Jason Cong ， Computer Science Department ， UCLA Presented.

ASIC/FPGA design flow. Design Flow Detailed Design Detailed Design Ideas Design Ideas Device Programming Device Programming Timing Simulation Timing Simulation.

Reconfigurable Architectures Greg Stitt ECE Department University of Florida.

LB Logic Block LB Logic Block LB Logic Block LB Logic Block LB Logic Block LB Logic Block LB Logic Block LB Logic Block LB Logic Block S/V block I/O Cell.

Penn ESE535 Spring DeHon 1 ESE535: Electronic Design Automation Day 5: February 2, 2015 Clustering (LUT Mapping, Delay)

Penn ESE535 Spring DeHon 1 ESE535: Electronic Design Automation Day 25: April 17, 2013 Covering and Retiming.

1 Architecture of Datapath- oriented Coarse-grain Logic and Routing for FPGAs Andy Ye, Jonathan Rose, David Lewis Department of Electrical and Computer.

SUBJECT : DIGITAL ELECTRONICS CLASS : SEM 3(B) TOPIC : INTRODUCTION OF VHDL.

A New Logic Synthesis, ExorBDS

Mapping into LUT Structures

Reconfigurable Computing

HDL Hardware Description Language

Digital Designs – What does it take

Presentation transcript:

FlowMap: An Optimal Technology Mapping Algorithm for Delay Optimisation in Lookup- Table Based FPGA Designs 04/06/ Presented by Qiwei Jin

Overview The paper and the authors. Some background information. The algorithm in detail. Results and Conclusion. Questions for discussion. 2

About the Paper Originally published in 1992, won IEEE Circuit & Systems Society best paper award in citations in total, 33 self. The first algorithm to solve a conventionally NP-hard depth minimisation problem in polynomial time. The algorithm is a key component in most commercial FPGA compilers. FlowMap-r and other more sophisticated algorithms published by the authors at the same year or later for both depth and area minimisation. 3

Jason Cong Chairman of Computer Science Department, UCLA. Was Assistant Professor in 1994 when this paper was published. Got Promoted to Associate Professor in the same year. His company Aplus was acquired by Magma in 2004 for "$13 million in stock, cash and incentives“. 4 Picture borrowed from Jason Cong’s homepage

Yuzheng Ding Very low profile person, no picture, no home page, not even on FaceBook. RA in UCLA for PhD when this paper was published. May have left university for work (Mentor Graphics) after graduation. Still working actively with Jason Cong, latest paper published in year

Background FPGA (Field-Programmable Gate Array): Programmable hardware. 6 Xilinx Virtex 5 FPGA

Background Cont. 7 For more information, go to Wayne Luk’s Custom Computing Course

Background Cont. FPGAs are essentially a bunch of wires and LUTs (Look-Up Tables) that can be configured to emulate the behaviour of a digital circuit. FPGAs can be configured by Hardware Description Language (HDL, such as VHDL). Based on the HDL, a netlist can be generated automatically by some algorithm (FlowMap!). 8

Background Cont. = 9 Addr.Value Input 1-Output LUT (16 entries in total)

Background Cont. Mappings from ASIC to FPGAs are not necessary one to one. The question is how to achieve the optimal condition? 10 =

Background Cont. Trade-offs: – Area (number of LUTs used) – Depth (delay of the circuit) FlowMap focuses on depth optimisation 11 depth

Depth Minimisation Example 12

The Key Idea of Depth Minimisation Try to pack as many gates in different levels into a LUT as possible. Number of LUT used (Area) is not the primary concern. The problem is equivalent to generating optimal code for expressions containing common subexpressions, hence NP-Hard.* Conventional method will decompose the Boolean network into a forest of trees before processing. FlowMap can find an optimal mapping directly from a Boolean network within polynomial time. Let’s see how. 13 * A. Aho, S. C. Johnson, “Optimal Code Generation for Expression Trees”, 23, 3, (1976).

Preliminaries Input(T) Cut (X, X) Node Cut Size Edge Capacity Edge Cut Size Whether a cut is K-feasible Height of a Cut

The FlowMap Algorithm 2 Phases – Node Labeling: define the optimal depth of the LUT mapping solution for N t. – LUT Mapping: generate the LUT network based on the labeling in the first phase.

Phase 1: Node Labelling 16

Phase 1: Node Labelling Cont. 17

Phase 2: LUT Mapping 18

Phase 2: LUT Mapping Cont. 19

The FlowMap Pseudocode 20

Enhancements Maximising Cut Volume During Mapping Postprocessing (flow-pack) Operations to reduce number of K-LUTs 21

Results 22

Conclusion The paper presents the first algorithm to compute a NP-hard problem in polynomial time. Compared to other algorithms FlowMap is about to reduce up to 7% of the LUT network and reduce up to 50% of the number of LUTs. 23

Questions It is claimed that a minimum height K-feasible cut can be found in O(Km) time, where K is the number of input of LUT and m is the number of edges of in the network. But it is not clear to me how it is derived. 24

Questions Cont. It would be interesting to see the time taken to compute the mapping for the testing cases with FlowMap vs. Other Algorithms. The testing cases are generally small in size, it would be more convincing to see some large size examples. 25