1. ECE 667 Synthesis and Verification of Digital Systems
Technology Mapping
(standard cells)
Slides adapted (with permission) from A. Kuehlmann, UC Berkeley 2003

2. Technology Mapping Where is it used Role Also called library binding
After technology independent optimization
Role
Assign logic functions to gates from custom library
Optimize for area, delay, power, etc.
Also called
library binding
Initial logic network
techn-independent
optimization
technology
mapping
Cell library
manufacturing
ECE 667 Synthesis & Verification - Technology Mapping (ASIC)

3. Technology Mapping – standard cells
Rule-Based [LSS]
Based on structural mapping [DAGON, MISII]
Represent each function of a network using a set of base functions
Typically the base is 2-input NANDs and inverters
The set should be functionally complete
This representation is called the subject graph.
Each gate of the library is likewise represented using the base set. This generates pattern graphs.
Represent each gate in all possible ways
Cover the subject graph with patterns
graph-based
binate covering
Based on Boolean matching (functional)
Use BDDs to find pattern matching
ECE 667 Synthesis & Verification - Technology Mapping (ASIC)

4. Technology-independent Optimization
Original logic network (16 literals):
t1 = a + bc;
t2 = d + e;
t3 = ab + d;
t4 = t1t2 + fg;
t5 = t4h + t2t3;
F = t5’.
Technology independent optimization (14 literals):
t1 = d + e;
t2 = b + h;
t3 = at2 + c;
t4 = t1t3 + fgh;
F = t4’;
d+e
b+h
t4’
at2 +c
t1t3 + fgh F
d+e
a+bc
t5’
t1t2 + fg F
ab+d
t4h + t2t3
ECE 667 Synthesis & Verification - Technology Mapping (ASIC)

5. Cell Library (library of gates)
Implement the optimized logic network using a set of gates which form a library
Each gate has a cost (area, delay, etc.)
ECE 667 Synthesis & Verification - Technology Mapping (ASIC)

6. Tree Covering Problem Given Define a cover of the subject tree:
a rooted binary tree T(V,E), called subject tree, and
a family of rooted pattern trees, each with some cost
Define a cover of the subject tree:
a partition of the edge set E, where each block of the partition induces a tree isomorphic to a pattern tree
i.e., a set of instances of the pattern trees must cover the subject tree without covering any edge more than once
Tree covering problem
Find a minimum cost covering of the subject graph by choosing from the collection of pattern graphs for all the gates in the library.
ECE 667 Synthesis & Verification - Technology Mapping (ASIC)

7. Subject Graph b’ h’ a d’ e’ h g f c F d+e b+h t4’ at2 +c t1t3 + fgh F
Subject graph of 2-input NANDs and invertors
ECE 667 Synthesis & Verification - Technology Mapping (ASIC)

8. Structural Approach Technology mapping problem:
A cover is a collection of pattern graphs such that:
every node of the subject graph is contained in one (or more) pattern graphs
each input required by a pattern graph is an output of some other graph (i.e. the inputs of one gate come as outputs of other gates.)
For minimum area, the cost of the cover is the sum of the areas of the gates in the cover.
Technology mapping problem:
Find a minimum cost covering of the subject graph by choosing from the collection of pattern graphs (from cell library).
Two phases of technology mapping:
Pattern matching (find all ways a library pattern covers the nodes in the subject graph)
Tree covering
ECE 667 Synthesis & Verification - Technology Mapping (ASIC)

9. Subject Graph f g d F e h b a c t1 = d + e; t2 = b + h; t3 = at2 + c;
t4 = t1t3 + fgh;
F = t4’;
ECE 667 Synthesis & Verification - Technology Mapping (ASIC)

10. Pattern Graphs for the IWLS Library
inv(1)
nand2(2)
nand3 (3)
(cost)
nor3 (3)
nor(2)
oai22 (4)
aoi21 (3)
xor (5)
ECE 667 Synthesis & Verification - Technology Mapping (ASIC)

11. Subject graph coveringF f g d e h b a c
t1 = d + e;
t2 = b + h;
t3 = at2 + c;
t4 = t1t3 + fgh;
F = t4’;
Total cost = 23
ECE 667 Synthesis & Verification - Technology Mapping (ASIC)

12. Better Covering F and2(3) f g aoi22(4) or2(3) d e h b Total cost = 18
nand2(2)
inv(1)
t1 = d + e;
t2 = b + h;
t3 = at2 + c;
t4 = t1t3 + fgh;
F = t4’;
Total cost = 18
ECE 667 Synthesis & Verification - Technology Mapping (ASIC)

13. Alternate Covering f nand3(3) g and2(3) oai21(3) d F e h b oai21 (3)
inv(1)
nand2(2)
t1 = d + e;
t2 = b + h;
t3 = at2 + c;
t4 = t1t3 + fgh;
F = t4’;
Total area = 15
ECE 667 Synthesis & Verification - Technology Mapping (ASIC)

14. Tech. mapping using DAG Covering
Input:
Technology independent, optimized logic network
Description of the gates in the library with their cost
Output:
Netlist of gates (from library) which minimizes total cost
General Approach:
Construct a subject DAG for the network
Represent each gate in the target library by pattern of DAG’s
Find an optimal-cost covering of subject DAG using the collection of pattern DAG’s
ECE 667 Synthesis & Verification - Technology Mapping (ASIC)

15. Tech. mapping using DAG covering
Complexity of DAG covering:
NP-hard
Remains NP-hard even when the nodes have out degree  2
If subject DAG and pattern DAG’s are trees, an efficient algorithm exists
Simpler problem: if the subject DAG and primitive DAG’s are trees
An efficient algorithm to find the best cover exists
Based on dynamic programming
First proposed for optimal code generation in a compiler
ECE 667 Synthesis & Verification - Technology Mapping (ASIC)

16. Dynamic Programming
An algorithmic method that solves an optimization problem by decomposing it into a sequence of decisions.
Such decisions lead to an optimum solution if the following Principle of Optimality is satisfied [Bellman 1957]:
An optimal sequence of decisions has the property that whatever the initial state and decisions are, the remaining decisions must constitute an optimal decision sequence w.r.to the state resulting from the first decision.
ECE 667 Synthesis & Verification - Technology Mapping (ASIC)

17. Dynamic Programming Simpler statement of Principle of Optimality
In an optimal sequence of decisions or choices each subsequence must also be optimal.
Typical recursive equation:
cost(i) = mink{ dik + cost(k) }
dik
cost(i) i ki
cost(ki) k1 kj
ECE 667 Synthesis & Verification - Technology Mapping (ASIC)

18. Dynamic Programming - example
Example: shortest path problem in a layered network
cost(i) = mink{ dik + cost(k) }
Step 1: going from Output(s) to Input(s), compute cost of each node
(+ mark the node k that gave minimum cost for i) 8 5 3 1 4 2 6 a b c d s t 5 9 7 3
Step 2: going from Input(s) to Ouput(s), select the node on critical path:
( s → c → a → t )
ECE 667 Synthesis & Verification - Technology Mapping (ASIC)

19. Dynamic Programming - example
Similarly, for node i at gate gi:
cost(i) = mink{cost(gi) + k cost(kj) } i gi k1 k2
k inputs to gi
ECE 667 Synthesis & Verification - Technology Mapping (ASIC)

20. Optimal Tree Covering by Trees
Partition subject graph into forest of trees
Cover each tree optimally using dynamic programming
Given:
Subject trees (networks to be mapped)
Forest of patterns (gate library)
Consider a node N of a subject tree
Recursive Assumption: for all children of N, a best cost match (which implements the node) is known
Cost of a leaf of the tree is 0.
Compute cost of each pattern tree which matches at N,
Cost = SUM of best costs of implementing each input of pattern
plus the cost of the pattern
Choose least cost matching pattern for implementing N
ECE 667 Synthesis & Verification - Technology Mapping (ASIC)

21. Optimum Area Algorithm
Algorithm OPTIMAL_AREA_COVER(node) {
foreach input of node {
OPTIMAL_AREA_COVER(input);// satisfies recurs. assumption }
// Using these, find the best cover at node
nodearea = INFINITY;
nodematch = 0;
foreach match at node {
area = matcharea;
foreach pin of match {
area = area + pinarea;
if (area < nodearea) {
nodearea = area;
nodematch = match;
ECE 667 Synthesis & Verification - Technology Mapping (ASIC)

22. Technology Mapping - example
Pattern trees (library)
F = (a’ (b+c))’ = a + b’ c’
and2 (4)
inv (2)
Subject tree (network)
aoi12 (10)
nand2 (10)
nand2 (3) a b c
or2 (5)
nand2 (7)
inv (2)
or2 (5)
aoi12 (6)
inv (2)
inv (2)
ECE 667 Synthesis & Verification - Technology Mapping (ASIC)

23. Tree Covering in Action
nand2 = 3
inv = 2
nand3 = 4
nand4 = 5
and2 = 4
aio21 = 4
oai21 = 4
Library:
(=cost)
nand2(3)
aoi21
nand2(8)
nand2(13)
inv(2)
inv(20)
aoi21(18)
inv(2)
nand4
inv(6)
and2(8)
nand2(21)
nand3(22)
nand4(18)
inv(5)
and2(4)
nand2(3)
nand2(21)
nand3(23)
nand4(22)
nand2(7)
nand3(4)
nand4
ECE 667 Synthesis & Verification - Technology Mapping (ASIC)

24. Complexity of Tree Covering
Complexity is controlled by finding all sub-trees of the subject graph which are isomorphic to a pattern tree.
Complexity of covering is linear in both size of subject tree and size of collection of pattern trees
But: for the overall mapping, must add complexity of matching
Complexity = O(nodes)*(complexity of matching)
ECE 667 Synthesis & Verification - Technology Mapping (ASIC)

25. Partitioning the Subject DAG into Trees
Trivial partition: break the graph at all multiple-fanout points
leads to no “duplication” or “overlap” of patterns
drawback - sometimes results in many of small trees
Leads to 3 trees
ECE 667 Synthesis & Verification - Technology Mapping (ASIC)

26. Partitioning the subject DAG into trees
Single-cone partition:
from a single output, form a large tree back to the primary inputs;
map successive outputs until they hit matched output formed from mapping previous primary outputs.
Duplicates some logic (where trees overlap)
Produces much larger trees, potentially better area results
output
ECE 667 Synthesis & Verification - Technology Mapping (ASIC)

27. Min-Delay Covering For trees: For DAGs: Combined objective
identical to min-area covering
use optimal delay values within the dynamic programming paradigm
For DAGs:
if delay does not depend on number of fanouts: use dynamic programming as presented for trees
leads to optimal solution in polynomial time
“we don’t care if we have to replicate logic”
Combined objective
e.g. apply delay as first criteria, then area as second
combine with static timing analysis to focus on critical paths
ECE 667 Synthesis & Verification - Technology Mapping (ASIC)

28. Summary Two approaches to technology mapping
DAG covering
Binate mapping
New approaches: combined logic decomposition and technology mapping
Lehman, Watanabe allgorithm [1994]
Efficiently encode a set on AND2/INV decompositions
Dynamically perform logic decomposition
Was implemented and used for commercial design projects (in DEC/Compac alpha)
ECE 667 Synthesis & Verification - Technology Mapping (ASIC)