Intel Process Technology Gaps June 2003 Intel Confidential Paula Goldschmidt IE- SBD Mgr.

Slides:



Advertisements
Similar presentations
10-1 McGraw-Hill/Irwin Copyright © 2010 by The McGraw-Hill Companies, Inc. All rights reserved.
Advertisements

18 July 2001 Work In Progress – Not for Publication 2001 ITRS Test Chapter ITRS Test ITWG Mike Rodgers Don Edenfeld.
More than Moore ITRS Summer Meeting 2008 July 14, 2008 San Francisco, CA.
Assembly and Packaging TWG
The Makers of the Microchip
Bringing the Voice of the Consumer Into Your Supply Chain Jake Barr Director, Consumer Driven Supply Network Global Mfg, Planning & Logistics The Procter.
2014 Annual Congress of the Federation of Canadian Municipalities May 31 st, 2014 Infrastructure Research.
Advancing Alternative Energy Technologies Glenn MacDonell Director, Energy Industry Canada Workshop on Alternatives to Conventional Generation Technologies.
Logic Process Development at Intel
Working With A Large Company Jean-Louis Trochu Texas Instruments May 2011.
ECE 6466 “IC Engineering” Dr. Wanda Wosik
Nanoscale structures in Integrated Circuits By Edward Mulimba.
PACIFIC CENTURY Presented by Group 1B. PACIFIC CENTURY Agenda 1)Background of PCCW 2)Industry Life Cycle 3)Key Strategies -Where to compete -How to compete.
Materials Management BUS 3 – 141 Quality and Specification Leveraging Technical Excellence Week of Aug 31, 2010.
Intel ® Research mote Ralph Kling Intel Corporation Research Santa Clara, CA.
Emerging Technologies – A Critical Review Presenter: Qufei Wu 12/05/05.
DRIVING INNOVATION AND ABILITY TO COMPETE THROUGH OUTSOURCING Anthony (Tony) C. Bernardo, Alloy Polymers Inc. NPE 2003 bernardo:
Supplier Selection A Four-Step Process Supplier Identification Supplier Evaluation Approved List Supplier Performance Monitoring Supplier Identification.
Per Andersson CEO. Tornado Market Growth A really big tornado is forming on the horizon. “Bigger than the world’s telephone network, more revolutionary.
Product/Service Name: Team Leader: Faculty / Research Alliance: Mobile Tel:
ECEn 191 – New Student Seminar - Session 5: Integrated Circuits Integrated Circuits ECEn 191 New Student Seminar.
MK Dutta September GMS- SME Business Networking- Challenges and Prospects Madhurjya Kumar Dutta Program Manager, Trade & Investment Mekong Institute.
1 VLSI and Computer Architecture Trends ECE 25 Fall 2012.
1. 2 IT innovations in specialized areas where competitors will have difficulty copying Excellence in design of processes and activities and how they.
1 CREATING A LEARNING ORGANIZATION AND AN ETHICAL ORGANIZATION STRATEGIC MANAGEMENT BUAD 4980.
Copyright © 2008 by The McGraw-Hill Companies, Inc. All rights reserved. McGraw-Hill/Irwin 1 Cost Management and Strategic Decision Making Evaluating.
Introduction Challenges of Managing in a Network Economy.
1 McGraw-Hill/Irwin Copyright © 2004, The McGraw-Hill Companies, Inc. All rights reserved. Chapter 9 Developing Business/Information Technology Strategies.
The Challenge of IT-Business Alignment
Operational Excellence and Sustainable Performance Improvement Date: 9 June, 2009.
ITRS Factory Integration Difficult Challenges Last Updated: 30 May 2003.
Chapter 2 Introduction to Cost Management Systems
Presented By : LAHSAINI Achraf & MAKARA Felipe.  Introduction  Difficult Challenges : > Difficult Challenges between 2013 – 2020 > Difficult Challenges.
Text Book: Silicon VLSI Technology Fundamentals, Practice and Modeling Authors: J. D. Plummer, M. D. Deal, and P. B. Griffin Class: ECE 6466 “IC Engineering”
NanoRelay Pros: High Ion:Ioff Excellent Ioff Robust to temperature/radiation Embedded memory (hysterisis) Potential for RF device and sensor and hybrid.
Quality Control Corp.. QCC Quality Control Corp n Privately Held, Incorp n Financially Independent n 2 Operating Divisions: QC Div. / QT Div. n.
Build the Right Team 1 Organize for Success 2 Build Coalition with Business Partners 3 Maintain Flexibility 4 Key Success Factors KSF 1.1: Relentlessly.
Group H: Krista, Christine, Sara, Dorothee. Agenda 3 Goals of Our Presentation To better understand how ERP has impacted Celestica’s operations To draw.
Integration of Tippecanoe Laboratories The right Resources, Competencies, Skills -- A post Acquisition Integration starts prior to signing Thomas Ayres.
Present – Past -- Future
Marv Adams Chief Information Officer November 29, 2001.
Chapter 7 Enterprise Resource Planning (ERP). Objectives After studying the chapter, students should be able to.. Explain definition of Enterprise Resource.
EE586 VLSI Design Partha Pande School of EECS Washington State University
EE141 © Digital Integrated Circuits 2nd Introduction 1 Principle of CMOS VLSI Design Introduction Adapted from Digital Integrated, Copyright 2003 Prentice.
VLSI Design System-on-Chip Design
Innovations for Sustainability Integrating Stakeholders into the Innovation Process Environmental Management Leadership Symposium Università Bocconi, Milano.
Cooperative Strategy Cooperative Strategy
12-CRS-0106 REVISED 8 FEB 2013 APO (Align, Plan and Organise)
The Business Case for Executive Assessment : Why Assessment in Challenging Times Can Enhance Productivity and Be a Talent “Game Changer” Linda Sharkey,
Michael Saucier - OSIsoft Cliff Reeves - Microsoft Your Portal to Performance An Introduction to the RtPM Platform Copyright c 2004 OSIsoft Inc. All rights.
CC311 Computer Architecture Chapter 1 Computer Abstraction & Technology.
Workshop synthesis Robert Judd General Secretary GERG GERG/MARCOGAZ Gas Sensor Workshop, Brussels, 27th February 2014.
Unifying Talent Management. Harnessing the Power of Workforce Intelligence in Talent Planning to Drive Business Performance.
Driving Innovation Fuel cells manufacturing and supply chain Proposed outline for competition for funding.
Best Practices for a Full Value Chain Approach Open Innovation Matthew C. Heim, Ph.D. President, NineSigma Inc.
Dirk Beernaert European Commission Head of Unit Nanoelectronics EC Programmes in Micro & nanoelectronics A way to a bright future? EU 2020, KET, H2020,
MOLETRONICS An Invisible technology Amit Dwivedi Ec 3rd Year
The Division includes two lines of effort:
Summary Remaining Challenges The Future Messages to Take Home.
Going on the Offensive Commit to building your competitive advantage until it is decisive Build from your most significant strengths and capabilities Attack.
BUSINESS DRIVEN TECHNOLOGY
TECHNOLOGY TRENDS.
INNOLABS CONTEST IDEA June 2018, Paris, France Organized by.
Overview of VLSI 魏凱城 彰化師範大學資工系.
Transistors on lead microprocessors double every 2 years Moore’s Law in Microprocessors Transistors on lead microprocessors double every 2 years.
Overview Why VLSI? Moore’s Law. Why FPGAs?
HIGH LEVEL SYNTHESIS.
Overview Why VLSI? Moore’s Law. Why FPGAs?
Presentation transcript:

Intel Process Technology Gaps June 2003 Intel Confidential Paula Goldschmidt IE- SBD Mgr.

Do not copy or transferIntel confidential Process Manufacturing -Technology Development Key Issues Technology scaling difficulty increasing New materials/architectures required vs. optional More complex core technologies (ie trigate transistors) Maintain 2 year process development cycle Increasing levels of process and device integration External constraints and competition increasing Declining ASP’s even though capital costs are increasing Growing competition Keep One Generation Ahead Leadership

LITHOGRAPHY IS THE MAJOR CHALLENGE

Do not copy or transferIntel confidential Litho Taxonomy Lensesmanufacturer EUV capability Materials forlensesManufacturing TrackManuf. Mask manuf.Mask RepairInspectioncapab.Mask writingSW Mask manuf.Mask RepairInspectioncapab.Mask writingSW Source – VLSI Research Feb 2003, First Call, Company websites New resists EUV light sources manufacturers

Intel Focused on Silicon Technology Merging Computing and Communications

Do not copy or transferIntel confidential Realizing The Vision Wireless Excellencein Silicon Research Logic Optical Biological Sensors Fluidics Mechanical Memory

Do not copy or transferIntel confidential : Intel I/E-SBD Collaboration Objectives: Enable One Generation Ahead (OGA) through Collaboration: Collaborate with Academic Research For Early engagement in Process/Tech development. Time and IP advantage. Improved supplier execution. Limited financial downside risk. Price and royalty benefits of supply. Collaborate with Start-up/Spin-off companies: Demonstrate enabling technology to fill Next technologies roadmap gaps Disruptive technologies to create roadmap options Intel Capital Team Intel Investment body to enable technologies availability

Do not copy or transferIntel confidential Silicon Technology Gaps –Extend Moore’s Law. Silicon base, varied toppings with new materials and devices –Develop more productive technology –Low power/high speed devices –Continue to introduce a new technology generation every two years

Do not copy or transferIntel confidential I/E-SBD areas of interest Alternatives to Silicon Nanotechnology Process & Fab Technology Assembly/Test Supply, Capacity & Components Start Materials TMG Process technology collaboration taxonomy MEMS +

Do not copy or transferIntel confidential Potential Areas of Interest In Si Technologies : 3-5 yrs to Market  Transistor Performance –High K –Low K –Interconnects –Structures  Litho EUV –Masks: manufacturing, cleaning, inspection  Memories –New Materials –New Structures  Nanotechnologies –Application Technologies/Integration into products

Do not copy or transferIntel confidential MEMS Potential Areas of Interest  Communication Devices –Performance –Reliability  MEMS packaging –Hermetic packaging

Do not copy or transferIntel confidential How to contact us  Send a Abstract of relevant projects to: –for Assembly/Test & MEMS  –for Litho/Yield/Defects & Clean room  –for Fab & Nanotechnologies  –For Investments 

Do not copy or transferIntel confidential Thanks