Read Only Memory DC A0A0 A 1 11 0 1 2 3 b1b1 b2b2 Programmable ROM DC A0A0 A 1 0 1 2 3 +v b1b1 b2b2 1 1 1 1 0 0 0 1 1 1 01 Fuse Mask-programmed ROM.

Slides:



Advertisements
Similar presentations
CS1104 – Computer Organization
Advertisements

Random-Access Memory (RAM)
컴퓨터구조론 교수 채수환. 교재 Computer Systems Organization & Architecture John D. Carpinelli, 2001, Addison Wesley.
Synchronous Sequential Logic
Programmable Logic PAL, PLA.
1 KU College of Engineering Elec 204: Digital Systems Design Lecture 9 Programmable Configurations Read Only Memory (ROM) – –a fixed array of AND gates.
Registers and Counters. Register Register is built with gates, but has memory. The only type of flip-flop required in this class – the D flip-flop – Has.
CPEN Digital System Design
EECC341 - Shaaban #1 Lec # 13 Winter Sequential Logic Circuits Unlike combinational logic circuits, the output of sequential logic circuits.
Parity. 2 Datasheets TTL:  CMOS: 
Asynchronous Sequential Circuits. 2 Asynch. vs. Synch.  Asynchronous circuits don’t use clock pulses  State transitions by changes in inputs  Storage.
Introduction to CMOS VLSI Design CAMs, ROMs, and PLAs
Chapter 3 Continued Logic Gates Logic Chips Combinational Logic Sequential Logic Flip Flops Registers Memory Timing State Machines.
Example: 7 Segment Displays BA DC\ xxxx 10 11xx Decimal Number Inputs Outputs DCBA abcdefg
Asynchronous Sequential Circuits

EE466:VLSI Design CAMs, ROMs, and PLAs. CMOS VLSI Design14: CAMs, ROMs, and PLAsSlide 2 Outline  Content-Addressable Memories  Read-Only Memories 
Chapter 3 Continued Logic Gates Logic Chips Combinational Logic Timing Sequential Logic Flip Flops Registers Memory State Machines.
Multiplexer MUX. 2 Multiplexer Multiplexer (Selector)  2 n data inputs,  n control inputs,  1 output  Used to connect 2 n points to a single point.
Lecture 13 Problems (Mano)
طراحی مدارهای منطقی نیمسال دوم دانشگاه آزاد اسلامی واحد پرند.
Reouven Elbaz – February 10 th, 2009 Office room: DC3576 ECE223.
Semiconductor Memories Lecture 1: May 10, 2006 EE Summer Camp Abhinav Agarwal.
Figure to-1 Multiplexer and Switch Analog
Introduction to Digital Logic Design Appendix A of CO&A Dr. Farag
PC BUS ? Programmic realisation Micro controller PC RAM CPU PORT ROM Timer ? Own micro circuit DescriptionDesign Technology for designing Micro circuits.
Random-Access Memory (RAM)
Chapter 5 Memory and Programmable Logic 5.1. Introduction 5.2. Random Access Memory 5.3. Memory Encoding 5.4. Read Only Memory 5.5. Programmable Logic.
Memory and Programmable Logic Dr. Ashraf Armoush © 2010 Dr. Ashraf Armoush.
Basic digital logic J. Christiansen, CERN - EP/MIC
Chapter 2Basic Digital Logic1 Chapter 2. Basic Digital Logic2 Outlines  Basic Digital Logic Gates  Two types of digital logic circuits Combinational.
ROM & PLA Digital Logic And Computer Design
Programmable Logic Devices
1 Lecture 9 Demultiplexers Programmable Logic Devices  Programmable logic array (PLA)  Programmable array logic (PAL)
CHAPTER 9 MULTIPLEXERS, DECODERS, AND PROGRAMMABLE LOGIC DEVICES
Digital Design: Principles and Practices
Chapter
Introduction to Sequential Logic Design Finite State-Machine Design.
Review of Digital Logic Design Concepts OR: What I Need to Know from Digital Logic Design (EEL3705)
Memory 10/27/081ECE Lecture. Memory Memory Types Using memory to implement logic functions 10/27/082ECE Lecture.
Testing of ROM. Functional faults: 1.Main SAF; 2.Amplifier SAF; 3.R/W line SAF; 4.Selection CS SAF; 5.Data line SAF; 6.Data line interruption; 7.Data line.
Programmable Logic Devices - I. Outline  Programmable Logic Devices  PN Diode Operation  AND Logic Arrays  OR Logic Arrays  Two-level AND-OR Arrays.
CS/COE0447 Computer Organization & Assembly Language
IC design options PLD (programmable logic device)
Lecture 24: 12/3/2002CS170 Fall CS170 Computer Organization and Architecture I Ayman Abdel-Hamid Department of Computer Science Old Dominion University.
Combinational Circuit Design. Digital Circuits Combinational CircuitsSequential Circuits Output is determined by current values of inputs only. Output.
Programmable logic devices. CS Digital LogicProgrammable Logic Device2 Outline PLAs PALs ROMs.
CSI-2111 Structure of Computers Ipage Combinational Circuits  Objectives : To recognize the principal types of combinational circuits  Adders.
Programmable Logic Devices. Principle of Operation: Example: X = A.B + A’.B’ requires that fuses f1 and f4 to be “blown”.
CEC 220 Digital Circuit Design Decoders, Encoders, & ROM Wed, February 19 CEC 220 Digital Circuit Design Slide 1 of 18.
1 CS/COE0447 Computer Organization & Assembly Language Logic Design Appendix C.
1 Chap 6. Memory and Programmable Devices Memory & Programmable Logic Device Definitions Memory –a collection of cells capable of storing binary.
Programmable Logic Devices
Mealy and Moore Machines Lecture 8 Overview Moore Machines Mealy Machines Sequential Circuits.
Gunjeet Kaur Dronacharya Group of Institutions. Outline Introduction Random-Access Memory Memory Decoding Error Detection and Correction Programmable.
Chapter- 9 Programmable Logic Devices DHADUK ANKITA ENRL NO Noble Engineering College- Junagadh.
Digital Design Lecture 14
Class Exercise 1B.
Recap DRAM Read Cycle DRAM Write Cycle FAST Page Access Mode
ECE 434 Advanced Digital System L03
Chapter 11 Sequential Circuits.
CPE/EE 422/522 Advanced Logic Design L02
ECE 434 Advanced Digital System L04
FIGURE 7.1 Conventional and array logic diagrams for OR gate
حافظه و منطق قابل برنامه ریزی
ECE434a Advanced Digital Systems L02
حافظه و منطق قابل برنامه ریزی
Semiconductor Memories
Combinational Circuits
Presentation transcript:

Read Only Memory DC A0A0 A b1b1 b2b2 Programmable ROM DC A0A0 A v b1b1 b2b Fuse Mask-programmed ROM

DC A0A v b1b1 b2b tension 2U 1 tension U 1 tension 0 The only fuse that falls under the voltage of 2U resulting in its melting Programming of EPROM A1A1

n pp Silicon floating gate Silicon select gate V ss V dd V gg EPROM array V dd WL i Wl i+1 BL i Bl i+1 00 EPROM, EEPROM and Flash

Combinational Circuits Boolean function x 1 x 2 x n y y = f (x 1,x 2,… x n ) Knowing the logical values of inputs at a certain moment of time enables us to calculate the value of the output by using the Boolean function. Dependence on the values of previous inputs does not exist. Sequential Circuits Boolean function + state x 1 x 2 x n y In order to determine the value of the output at a certain moment of time it is necessary to know both the values of the inputs at a certain moment of time as well as state that is dependent on the values of the previous inputs. Clock input t determines when transition from one state to another takes place. t Output function Transition function Memory x 1 x n y1y1 Old state t New state amam asas Use of ROM in realising the hardware ymym... Realisation of combinational circuits in ROM.

Address X4X4 X3X3 X2X2 X1X ROM Example: Running of a segment indicator by ROM.

Combinational circuit InputsOutputs Memory Old state New state t (clk) Realisation of a synchronous sequential circuit on ROM

ROM InputsOutputs Direct Feedback ROM Inputs Outputs Registered Feedback Register t (clk) Feedback

ROM a0a0 a1a1 a2a2 a3a3 a4a4 clk o1o1 o2o2 o3o3 o4o4 etc... Example. 4-bit synchronous counter

ROM a0a0 a1a1 a2a2 clk o0o0 o1o1 o2o2 o3o3 x1x1 z1z1 z2z2 y1y1 y2y2 ab c / y 1 y 2 x 1 / y 1 y 2 - / y 1 y 2 x 1 / y 1 y 2 Beginning y 1 y 2 a b c x1x1 a End c Realisation of a synchronous automaton on ROM buffered with register

a b c - o0o0 o1o1 o2o2 o3o3 z 2 z 1 x 1 ROM table of an automaton

S0S0 S3S3 S2S2 S1S1 x 1 x 2 /v 1 x 1 x 2 /v 6 x 1 x 2 /v 7 x 1 x 2 /v 12 x 1 x 2 /v 3 x 1 x 2 /v 4 x 1 x 2 /v 9 x 1 x 2 /v 10 x 1 x 2 /v 2 x 1 x 2 /v 5 x 1 x 2 /v 7 x 1 x 2 /v Example ROM a0a0 a1a1 a2a2 a3a3 x1x1 o1o1 o2o2 o3o3 x2x2 onon Outputs State Realisation of an asynchronous automaton on ROM

Inputs State`State Outputs of the automaton ROM address inputs ROM data outputs ROM table

y 1 = x 3 x 2 x 1 + x 3 x 2 x 1 + x 3 x 2 = x 3 x 2 x 1 + x 3 x 2 x 1 + x 3 x 2 x 1 + x 3 x 2 x 1 y 2 = x 3 x 2 x 1 + x 3 x 2 = x 3 x 2 x 1 + x 3 x 2 x 1 + x 3 x 2 x 1 DC x1x1 a0a0 x2x2 a1a1 x3x3 a3a y1y1 y2y2 Decoder realises all possible conjunctions from all input variables. In case of the following example four different conjunctions should be realised. Decoder as a realiser of conjunctions

&1 1 1 A B C & & & & & & & Decoder realises all possible conjunctions from all input variables Decoder

111 +V y1y1 y2y2 y m x 1 x 2 x n + V Buffer ANDOR x 1 x 2 x n y1y1 y2y2 y m Programmable arrays. PLA - Programmable Logic Array, PAL - Programmable Array Logic

1 +V... +V y1y1 y2y2 y m x 1 x 2 x n Buffer NOR x 1 x 2 x n y1y1 y2y2 y m V 0 0 NOR – NOR array

Buffer AND – fixed (decoder) OR – programmable y1y1 y2y2 y m Buffer AND – programmable OR – programmable x 1 x 2 x n y1y1 y2y2 y m Buffer AND – programmable OR – fixed x 1 x 2 x n y1y1 y2y2 y m ROM – Read Only Memory PLA – Programmable Logic Array PAL – Programmmable Array Logic Comparison of ROM,PAL and PLA

111 +V x 3x 3 x 2 x 1x 1 0 y 1 y 2 Example. y 1 = x 3 x 2 x 1 + x 3 x 2 x 1 + x 2 x 1 y 2 = x 3 x 2 x 1 + x 2 x 1 Realisation of a combination circuit on a PLA/PAL type of array.

PLA/PAL Memory x 1 x n y1y1 Old state t New state amam asas ymym... Output function transition function Output function Transition function Memory x 1 x n y1y1 Old state t New state amam asas ymym... Realisation of a sequential circuit on a PAL/PLA type of array.