1. Recap DRAM Read Cycle DRAM Write Cycle FAST Page Access Mode
Same row different columns

2. Row Select 0 Select 1 Select 2 Select n-1 Select n Column Select 7
Comparator
Reference
Active Load +V
Row
Select 0
Select 1
Select 2
Select n-1
Select n
Column
Select 7
Data
Out 0
Out 1
Out 7
Stored
Logic 0
Logic 1
Output

3. A summary of Memory Types
Non-Volatile
High Density
One-Transistor Cell
In-System Write ability
SRAM No
Yes
DRAM
ROM
EPROM
EEPROM
FLASH

4. Devices A and B operating at same data rates

5. FIFO Memory connecting two communicating devices

6. Writing and Reading from FIFO Buffer

7. FIFO Implementation using four 8-bit Shift Registers
Input
Buffer
Data
Output
Four 8-bit Shift Registers
Shift
Register
Control
Logic
Ready

8. Implementation of a FIFO buffer using RAM

9. Digital Logic & Design
Dr. Waseem Ikram
Lecture 42

10. Recap DRAM Burst Refresh DRAM Distributed Refresh RAS only refresh
1024 row refreshed in 8 ms
DRAM Distributed Refresh
single row refreshed in 7.8 microsec
RAS only refresh
RAS goes low
CAS remains inactive
External counter provides row refresh addresses
CAS before RAS refresh
CAS goes low before RAS
Activates the internal counter to provide row refresh addresses

11. Recap
DRAM Types
FAST Page Mode
Extended Data Output
Synchronous DRAM

12. Recap ROM ROM Types Cell implementation of a Mask ROM
EPROM (UV EPROM & EEPROM)
Cell implementation of a Mask ROM
Transistor gate connected to row
Transistor column connected to column
General structure of ROM
Address decoder
Transistor array

13. Recap 256 x 4 ROM implementation ROM applications
Arrange in 32 rows and 32 columns
8 columns (groups) of 4-bit values
4 mux (8x1) at column
ROM applications
Conversion Tables
Data Tables
ROM Read cycle and access time

14. Recap PROM structure UV EPROM Programming EEPROM
Transistor output connected to column through a fuse
UV EPROM Programming
Vpp signal connected to high DC
PGM signal pulsed
EEPROM

15. Recap FLASH Operations with Flash Memory Programming Operation
Read/Write
non-volatile
high density
fast access time
cost effective
Operations with Flash Memory
Programming Operation
Read Operation
Erase Operation

16. FLASH Structure FLASH Structure (fig 1) Common Drain lines
Common Source lines (column select lines)
Row select activates all cells
Current flows through common drain line to active load
Voltage drop across active load compared with reference voltage
High output indicates 0 stored and vice versa

17. Memory Summary & Special Memory Types
FIFO Memory
Keyboard buffer Example
Connecting two devices communicating at different data rates
Direct connection (fig 2a)
Connection through buffer (fig 2b)
Buffer contents writing/reading (fig 2c)

18. FIFO Implementation FIFO Implementation using shift registers (fig 3)
four 8-bit shift registers store eight nibbles
Control circuitry to control
shift registers
Input and output buffers
FIFO Implementation using Memory (fig 4)