1 Inverter Layout

2 TX Gate: Layout VDD VSS VO Vi C CCC For data path structure P+ N+

3 Transmission Gate Layout

4 NAND Gates: Layout Layout Transistors in Series Transistors in Parallel

5 NAND Gates: Layout A B X Metal II Via VDD GND

6 NAND Gate Layout

7 Simulation results of CMOS 2-input NAND gate DC characteristics Active area Total area Static curren t V OH V OL V IH V IL NM L NM H um um volts 0 volt1.42 volts 0.87 volts 1.88 volts AC characteristics t PLH min t PHL min t P min t PLH max t PHL max t P max t r min t f min t r max t f max Averag e power Peak Power 0.15 ns 0.03 ns 0.09 ns 0.18 ns 0.05 ns ns 0.15 ns 0.14 ns ns 0.15 ns 0.43 mw 0.5 mw

8 simulation waveforms of NAND gate

9 NOR Gate: Layout AB X V DD GND

10 NOR Gate Layout

11 Waveform of the CMOS 2-input NOR gate.

12 DC characteristics Active area Total area Static current V OH V OL V IH V IL NM L NM H um um volts0 volts1.57 volts 0.95 volts 1.73 volts AC characteristics t PLH min t PHL min t P min t PLH max t PHL max t P max t r min t f min t r max t f max Average power Peak Power 0.18 ns 0.05 ns ns 0.2 ns 0.07 ns ns 0.2 ns 0.15 ns 0.24 ns 0.16 ns 0.45 mw0.6 mw Simulation results of CMOS 2-input NOR gate

13 Analysis and Design of Complex Gate A B C D E F VDD GND OUT N-well Analysis 1. Construct the schematic 2. Determine the logic function. 3. Determine transistor sizes. 4. Determine the input pattern to cause slowest and fastest operations. 5. Determine the worst case rise delay (t PLH )and fall delay (t PHL ) 6. Determine the best case rise and fall delays.

14 DFF Layout

15 Fundamental Cell Design General Considerations  Static logic;  Select aspect ratio of gates for example:

16 Cell Simulation: 2-input NAND gate

17 2-input NAND gate, Layout

18 2-input NAND gate, Simulation

19 2-input NAND gate, DC Characteristics Active area (um 2 ) Total area (um 2 ) Static current (uA) V OH (V) V OL (V) V IH (V) V IL (V) NM H (V) NM L (V)

20 2-input NAND gate, AC Characteristics t PLH min (ns) t PHL min (ns) t P min (ns) t PLH max (ns) t PHL max (ns) t P max (ns) t r min (ns) t f min (ns) t r max (ns) t f max (ns) Average power (mW) Peak power (mW)

21 2-input AND gate

22 2-input AND gate, layout

23 2-input AND gate, simulation

24 2-input AND gate, DC Characteristics Active area (um 2 ) Total area (um 2 ) Static curren t(uA) V OH (V) V OL (V) V IH (V) V IL (V) NM H (V) NM L (V)

25 2-input AND gate, Ac Characteristics t PLH min (ns) t PHL min (ns) t P min (ns) t PLH max (ns) t PHL max (ns) t P max (ns) t r min (ns) t f min (ns) t r max (ns) t f max (ns) Aver. power (mW) Peak power (mW)

26 3-input NAND gate, Design

27 3-input NAND gate. layout

28 3-input NAND gate, simulation

29 3-input NAND gate, DC Characteristics Active area (um 2 ) Total area (um 2 ) Static current (uA) V OH (V) V OL (V) V IH (V) V IL (V) NM H (V) NM L (V)

30 3-input NAND gate, AC Characteristics t PLH min (ns) t PHL min (ns) t P min (ns) t PLH max ns t PHL max (ns) t P max (ns) t r min ns t f min (ns) t r max (ns) t f max (ns) Av. powe r (mW) Peak power (mW)

31 3-input AND gate, Design

32 3-input AND gate, layout

33 3-input AND gate, simulation

34 3-input AND gate, Dc Characteristics Active area (um 2 ) Total area (um 2 ) Static current (uA) V OH (V) V OL (V) V IH (V) V IL (V) NM H (V) NM L (V)

35 3-input AND gate, Ac Characteristics t PLH min (ns) t PHL min (ns) t P min (ns) t PLH max (ns) t PHL max (ns) t P max (ns) t r min (ns) t f min (ns) t r max (ns) t f max (ns) Average power (mW) Peak power (mW)

36 2-input NOR gate, Design

37 2-input NOR gate, Layout

38 2-input NOR gate, Simulation

39 2-input NOR gate, DC Characteristics Active area (um 2 ) Total area (um 2 ) Static current (uA) V OH (V) V OL (V) V IH (V) V IL (V) NM H (V) NM L (V)

40 2-input NOR gate, Ac Characteristics t PLH min (ns) t PHL min (ns) t P min (ns) t PLH max (ns) t PHL max (ns) t P max (ns) t r min ns t f min (ns) t r max (ns) t f max (ns) Av. power (mW) Peak power (mW)

41 2-input OR gate, Design

42 2-input OR gate, Layout

43 2-input OR gate, Simulation

44 2-input OR gate, DC Characteristics Active area (um 2 ) Total area (um 2 ) Static curren t(uA) V OH (V) V OL (V) V IH (V) V IL (V) NM H (V) NM L (V)

45 2-input OR gate, AC Characteristics t PLH min (ns) t PHL min (ns) t P min (ns) t PLH max (ns) t PHL max (ns) t P max (ns) t r min (ns) t f min (ns) t r max (ns) t f max (ns) Av. power (mW) Peak power (mW)

46 3-input NOR gate, Design

47 3-input NOR gate, Layout

48 3-input NOR gate, Simulation

49 3-input NOR gate, DC Characteristics Active area (um 2 ) Total area (um 2 ) Static curre nt(uA) V OH (V) V OL (V) V IH (V) V IL (V) NM H (V) NM L (V)

50 3-input NOR gate, AC Charcarteristics t PLH min (ns) t PHL min (ns) t P min (ns) t PLH max (ns) t PHL max (ns) t P max (ns) t r min (ns) t f min (ns) t r max (ns) t f max (ns) Av. power (mW) Peak power (mW)

51 3-input OR gate, Design

52 3-input OR gate, Layout

53 3-input OR gate, Simulation

54 3-input OR gate, DC Characteristics Active area (um 2 ) Total area (um 2 ) Static current (uA) V OH (V) V OL (V) V IH (V) V IL (V) NM H (V) NM L (V)

55 3-input OR gate, AC Characteristics t PLH min (ns) t PHL min (ns) t P min (ns) t PLH max (ns) t PHL max (ns) t P max (ns) t r min (ns) t f min (ns) t r max (ns) t f max (ns) Av. power (mW) Peak power (mW)

56 4-input OR gate, Design

57 4-input OR gate, Layout

58 4-input OR gate, Simulation

59 4-input OR gate, DC Characteristics Active area (um 2 ) Total area (um 2 ) Static current (uA) V OH (V) V OL (V) V IH (V) V IL (V) NM H (V) NM L (V)

60 4-input OR gate, AC Characteristics t PLH min (ns) t PHL min (ns) t P min (ns) t PLH max (ns) t PHL max (ns) t P max (ns) t r min (ns) t f min (ns) t r max (ns) t f max (ns) Av. power (mW) Peak power (mW)

61 2-input XOR gate, Design

62 2-input XOR gate, Layout

63 2-input XOR gate, Simulation

64 2-input XOR gate, DC Characteristics Active area (um 2 ) Total area (um 2 ) Static current (uA) V OH (V) V OL (V) V IH (V) V IL (V) NM H (V) NM L (V)

65 2-input XOR gate, AC Characteristics t PLH min (ns) t PHL min (ns) t P min (ns) t PLH max (ns) t PHL max (ns) t P max (ns) t r min (ns) t f min (ns) t r max (ns) t f max (ns) Av. power (mW) Peak power (mW)

66 3-input XOR gate, Design

67 3-input XOR gate, Layout

68 3-input XOR gate, Simulation

69 3-input XOR gate, DC Characteristics Active area (um 2 ) Total area (um 2 ) Static current (uA) V OH (V) V OL (V) V IH (V) V IL (V) NM H (V) NM L (V)

70 3-input XOR gate, AC Characteristics t PLH min (ns) t PHL min (ns) t P min (ns) t PLH max (ns) t PHL max (ns) t P max (ns) t r min (ns) t f min (ns) t r max (ns) t f max (ns) Av. power (mW) Peak power (mW)

71 3-input XNOR gate, Design

72 3-input XNOR gate, Layout

73 3-input XNOR gate, Simulation

74 3-input XNOR gate, DC Characteristics Active area (um 2 ) Total area (um 2 ) Static current (uA) V OH (V) V OL (V) V IH (V) V IL (V) NM H (V) NM L (V)

75 3-input XNOR gate, AC Characteristics t PLH min (ns) t PHL min (ns) t P min (ns) t PLH max (ns) t PHL max (ns) t P max (ns) t r min (ns) t f min (ns) t r max (ns) t f max (ns) Average power (mW) Peak power (mW)

76 Positive-Edge-triggered D Flip-Flop with Reset

77 Positive-Edge-triggered D Flip-Flop with Reset

78 Positive-Edge-triggered D Flip-Flop with Reset

79 Positive-Edge-triggered D Flip-Flop with Reset parameterminimumtypicalmaximumunit Clock frequency MHz t PLH Reset to Q ns t PHL Reset to Q ns t PLH CLK to Q ns t PHL CLK to Q ns Width of clock pulse ns Width of Reset pulse ns Setup time0.3 ns Hold time0.1 ns Average power dissipation at 1000MHz CLK mW

80 Positive-Edge-triggered D Flip-Flop with Preset

81 Positive-Edge-triggered D Flip-Flop with Preset

82 Positive-Edge-triggered D Flip-Flop with Preset

83 Positive-Edge-triggered D Flip-Flop with Preset parameterminimumtypicalmaximumunit Clock frequency MHz t PLH SET to Q ns t PHL SET to Q ns t PLH CLK to Q ns t PHL CLK to Q ns Width of clock pulse ns Width of SET pulse ns Setup time0.3 ns Hold time0.15 ns Average power dissipation at 1000MHz CLK mW

84 Positive-Edge-triggered D Flip-Flop with Clear and Load

85 Positive-Edge-triggered D Flip-Flop with Clear/ Load

86 Positive-Edge-triggered D Flip-Flop with Clear

87 Positive-Edge-triggered D Flip-Flop with Clear parameterminimumtypicalmaximumunit Clock frequency MHz t PLH CLR to Q ns t PHL CLR to Q ns t PLH CLK to Q ns t PHL CLK to Q ns Width of clock pulse ns Width of clear pulse ns Setup time0.5 ns Hold time0.2 ns Average power dissipation at 1000MHz CLK mW

88 Positive-Edge-triggered D Flip-Flop with Preset and Load

89 Positive-Edge-triggered D Flip-Flop with Preset and Load

90 Positive-Edge-triggered D Flip-Flop with Preset and Load