1. 5x5 Pixel Array Status 28 January 2004
Sam Burke
Sean Stromberg
UCSB HEP Group
UCSB ASIC BiWeekly Status Meeting

2. ASIC Progress Working on basic Inverter Layout using L-Edit
Gaining experience with design rules
Beginning of Cell Library
UCSB ASIC BiWeekly Status Meeting

3. Inverter Layout Revised AMI 035 Inverter Layout
12 um x 4.5um cell size
54 um^2 area
Lp=0.35u, Wp=2.4u
Ln=0.35u, Wn=0.8u
no DRC errors
UCSB ASIC BiWeekly Status Meeting

4. Inverter Performance Timing Performance with one inverter load
Tlh=62ps
Thl=93ps
UCSB ASIC BiWeekly Status Meeting

5. 3rd Revision
Revised Inverter accommodates Nfet substrate contact and N-Well to the edge of cell
12x4.5um cell
Blue: Metal1
Red: Poly1
Green: Active
Pink: P+
Yellow: N Well
Lt Green:Active
Blk squares: Contact
Wht #1: Via1
Gray: Metal2
Note: N+ not drawn?
UCSB ASIC BiWeekly Status Meeting

6. Relative Size of Cell Human Hair 250um Pixel
17 Inverter
Cells
Human Hair
80um/4.5um = 17 Inverter cells
250um Pixel
250*250um^2 / 12*4.5um^2=1157 inverters under one pixel
Human Hair
80 um Dia
UCSB ASIC BiWeekly Status Meeting

7. D Flip Flop with /Rst
UCSB ASIC BiWeekly Status Meeting

8. DFFR Net List
UCSB ASIC BiWeekly Status Meeting

9. DFFR Timing
Td=588 ps
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10. DFFR Simulation Results
Ts: Setup Time > 0.4ns
Th: Hold Time > 0.1ns
Tclk-min: Minimum clock pulse width > 0.35ns
Fclk-max: Max Clock Freq < 980 Mhz
Td: Delay Time <0.5ns
Tc: Clear Time >0.4ns
Size [4*4.5+4*4.5+2*6]*12=48*12=576um^2
Note: 10 ps rise times on test clock
UCSB ASIC BiWeekly Status Meeting

11. Future Plans Start creating new Cell Library NMOS & PMOS Transistors
Inverter1 (done!)
Transmission Gate
NAND Gate
NOR Gate
D Flip Flop
D Flip Flop with Clear
UCSB ASIC BiWeekly Status Meeting