Asynch 1.1 Asynchronous Counters 1 ©Paul Godin Last Edit Sept 2009

Asynch1.2 Binary Counting If one looks at the changes in individual bits of a binary count from one value to the next, a frequency pattern emerges ↓↓↓

Asynch1.3 Binary Counting ↓↓↓ ½ f ¼ f f Each more significant digit has half the frequency of the previous digit. A divide-by-two frequency divider can be used to build a counter.

Asynch1.4 Frequency Division A device that divides the input frequency by 2 is a toggling JK flip-Flop Clk Q T T T J K Q Q 1 1

Asynch1.5 Asynchronous Counter To count in binary, the frequency of each more significant bit needs to divide the previous bit’s frequency by 2.

Asynch1.6 Dividing Add a JK Flip-Flop to the output of the first to divide by another 2. This last output divides the original clock by 4: Clk A B Note that one flip-flop is required for each bit of the binary number.

Asynch1.7 4-bit Binary Counter Note the labeling standard for counters. The LSB is always “A”

Asynch1.8 Asynchronous The counter bits are not clocked in synchronization; the source is applied to the first flip-flop only. This counter design is therefore asynchronous (not synchronous). It takes time for the clock edge to work its way through each flip-flop. Propagation delay is the cause of this effect. Because of the output pattern where the edge works its way through each flip-flop, asynchronous counters are also known as Ripple Counters.

Asynch1.9 Timing Diagrams It is important to remember to look at the state of the inputs just before the edge when drawing timing diagrams. When looking at the timing diagram, remember to identify the MSB and the LSB. The LSB is the Flip- Flop closest to the external clock input.

Asynch1.10 Reading a Counter Timing Diagram Based on the observed pattern, the least significant bit (LSB) is represented at the top of the timing diagram and the MBB is at the bottom. The values must be read from the bottom up (MSB to LSB) LSB MSB

Asynch1.11 Examples

Asynch1.12 Draw the timing diagram for the following counter: Example #1

Asynch1.13 Complete the State Diagram for the previous example: 000 Example #1

Asynch1.14 Complete the State Table for the previous example: Example #1

Asynch1.15 Questions  Identify and describe the counter in example 1. Truncated or Full sequence? Up or Down Synchronous or Asynchronous? Number of bits? Starting Point? Edge? Example #1

Asynch1.16 Example #2 Draw the timing diagram for the following counter:

Asynch1.17 Example #2 000 Complete the State Diagram for the previous example:

Asynch1.18 Complete the State Table for the previous example: Example #2

Asynch1.19 Questions  Identify and describe the counter in example 2. Truncated or Full sequence? Up or Down Synchronous or Asynchronous? Number of bits? Starting Point? Edge?  What are the differences from the counter in the first example? Example #2

Asynch1.20 ©Paul R. Godin prgodin gmail.com END