Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Topics n Interconnect design. n Crosstalk. n Power optimization.

Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Interconnect n Even assuming logic structure is fixed, we can: –change wire topology; –resize wires; –add buffers; –size transistors.

Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Multipoint nets n Two-point nets are easy to design. n Multipoint nets are harder: –How do we connect all the pins using two-point connections?

Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Styles of wiring trees source sink 2 sink 1 Spanning tree Steiner tree Steiner point

Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Sized Steiner tree source sink 2 sink 1 Feeds both branches Smaller currents in each branch

Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Buffer insertion in wiring trees n More complex than placing buffers along a transmission line: –complex topology; –unbalanced trees; –differing timing requirements at the leaves.

Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Van Ginneken algorithm n Given: –placements of sources and sinks; –routing of wiring tree. n Place buffers within tree to minimize the departure time at the source to meet all the sink arrival times: –T source = min i (T i -D i ) –T i = arrival time at node i, D i = delay to node I.

Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Delay calculation n Use Elmore model to compute delay along path from source to sink.

Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Recursive delay calculation n Recursively compute Elmore delay through the tree. –Start at sinks, work back to source. –r, c are unit resistance/capacitance of wire. –L k is total capacitive load of subtree rooted at node k.

Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Modifying the tree n Add a wire of length l at node k: –T k ’ = T k - r/L k - 0.5rcl. –L k ’ = L k + cl. n Buffer node k: –T k ’ = T k - D buf - R buf L k. –L k ’ = C buf. n Join two subtrees m and n at node k: –T k ’ = (T m, T n ). –L k ’ = L m + L n.

Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Crosstalk n Capacitive coupling introduces crosstalk. n Crosstalk slows down signals to static gates, can cause hard errors in storage nodes. n Crosstalk can be controlled by methodological and optimization techniques.

Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Coupling and crosstalk n Crosstalk current depends on capacitance, voltage ramp. w1w2 CcCc icic t

Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Crosstalk analysis n Assume worst-case voltage swings, signal slopes. n Measure coupling capacitance based on geometrical alignment/overlap. n Some nodes are particularly sensitive to crosstalk: –dynamic; –asynchronous.

Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Coupling situations sig1 axr better worse bus[0] bus[1] bus[2]

Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Layer-to-layer coupling n Long parallel runs on adjacent layers are also bad. bus[0] siga SiO 2

Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Methodological solutions n Add ground wires between signal wires: –coupling to V SS, a stable signal, dominates; –can use V SS to distribute power, so long as power line is relatively stable. n Extreme case—add ground plane. Costs an entire layer, may be overkill.

Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Ground wires V SS sig1 V SS sig2 V SS

Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Crosstalk and signal routing n Can route wires to minimize required adjacency regions. n Take advantage of natural holes in routing areas to decouple signals. n Minimizes need for ground signals.

Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Crosstalk routing example n Channel:

Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Assumptions n Take into account coupling only to wires in adjacent tracks. n Ignore coupling of vertical wires. n Assume that coupling/crosstalk is proportional to adjacency length.

Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Bad routing

Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Good routing

Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Crosstalk analysis n Want to estimate delays induced by crosstalk. n Effect of coupling capacitance C c depends on relative transitions. –Aggressor changes, victim does not: C c. –Aggressor, victim move in opposite directions: 2C c. –Aggressor, victim move in same direction: 0.

Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Crosstalk analysis, cont’d. n Coupling effects depend on relative switching time of nets. n Must use iterative algorithm to solve for coupling capacitances and delays.

Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Power optimization n Glitches cause unnecessary power consumption. n Logic network design helps control power consumption: –minimizing capacitance; –eliminating unnecessary glitches.

Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Glitching example n Gate network:

Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Glitching example behavior n NOR gate produces 0 output at beginning and end: –beginning: bottom input is 1; –end: NAND output is 1; n Difference in delay between application of primary inputs and generation of new NAND output causes glitch.

Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Adder chain glitching bad good

Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Explanation n Unbalanced chain has signals arriving at different times at each adder. n A glitch downstream propagates all the way upstream. n Balanced tree introduces multiple glitches simultaneously, reducing total glitch activity.

Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Signal probabilities n Glitching behavior can be characterized by signal probabilities. n Transition probabilities can be computed from signal probabilities if clock cycles are assumed to be independent. n Some primary inputs may have non- standard signal probabilities— control signal may be activated only occasionally.

Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Delay-independent probabilities n Compute output probabilities of primitive functions: –P NOT = 1 - P in –P OR = 1 -  P i ) –P AND =  P i n Can compute output probabilities of reconvergent fanout-free networks by traversing tree.

Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Delay-dependent probabilities n More accurate estimation of glitching. Glitch accuracy depends on accuracy of delay model. n Can use simulation-style algorithms to propagate glitches. n Can use statistical models coupled with delay models.

Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Power estimation tools n Power estimator approximates power consumption from: –gate network; –primary input transition probabilities; –capacitive loading. n May be switch/logic simulation based or use statistical models.

Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Factorization for low power n Proper factorization reduces glitching. badgood

Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Factorization techniques n In example, a has high transition probability, b and c low probabilities. n Reduce number of logic levels through which high-probability signals must travel in order to reduce propagation of glitches.

Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Layout for low power n Place and route to minimize capacitance of nodes with high glitching activity. n Feed back wiring capacitance values to power analysis for better estimates.