A Novel Digitization Scheme with FPGA-based TDC for Beam Loss Monitors Operating at Cryogenic Temperature Wu, Jinyuan, Arden Warner Fermilab Oct. 2011

Oct. 2011, Wu Jinyuan, Fermilab A Novel Digitization Scheme with FPGA TDC for BLM Typical Digitization Scheme for Recycling Integrators 2 Recycling Integrator Counter T Q I = N*Q/T

Oct. 2011, Wu Jinyuan, Fermilab A Novel Digitization Scheme with FPGA TDC for BLM Not Too Many Pulses to Count 3

Oct. 2011, Wu Jinyuan, Fermilab A Novel Digitization Scheme with FPGA TDC for BLM Digitization Scheme Using TDC 4 T Q I = Q/dt TDC c0 c90 c180 c270 Encoder Recycling Integrator dt

TDC Implemented with FPGA Oct. 2011, Wu Jinyuan, Fermilab A Novel Digitization Scheme with FPGA TDC for BLM 5

Oct. 2011, Wu Jinyuan, Fermilab A Novel Digitization Scheme with FPGA TDC for BLM 6 Multi-Sampling TDC in FPGA c0 c90 c180 c270 c0 Multiple Sampling Clock Domain Changing Trans. Detection & Encode Q0 Q1 Q2 Q3 QF QE QD c90 Coarse Time Counter DV T0 T1 TS Ultra low-cost. Sampling rate: 250 MHz x4 phases = 1 GHz. LSB = 1.0 ns. 4Ch Logic elements with non-critical timing are freely placed by the fitter of the compiler. This picture represent a placement in Cyclone FPGA

The Sampling Portion of the 1 ns TDC Oct. 2011, Wu Jinyuan, Fermilab A Novel Digitization Scheme with FPGA TDC for BLM 7

The Simulation of the 1 ns TDC Oct. 2011, Wu Jinyuan, Fermilab A Novel Digitization Scheme with FPGA TDC for BLM 8 CK250 IN

Oct. 2011, Wu Jinyuan, Fermilab A Novel Digitization Scheme with FPGA TDC for BLM 9 If You Want to Try: Larger System The KAEN V1495 module is a trigger module with a Cyclone FPGA. A firmware with 96 TDC channels plus trigger tables has been actually implemented. For pure TDC, 128 channels can be fit into the FPGA. V1495 $3800+2*537

Oct. 2011, Wu Jinyuan, Fermilab A Novel Digitization Scheme with FPGA TDC for BLM 10 If You Want to Try: Small System The FPGA on the Starter Kit is fairly powerful. More than 16 pairs LVDS I/O can be accessed via the daughter card. FPGA can fit 32 channels but implementing 16 channels is more practical given the I/O pairs. TDC data are stored in the RAM on the board and can be readout via USB. A good solution for small experiment systems as well as student labs. DK-START-3C25N Cyclone III FPGA Starter Kit $211 THDB-H2G (HSMC to GPIO Daughter Board) $50 Resolution: ns (LSB) with Multi-Sampling Scheme Resolution: 40 ps (LSB) with Wave Union TDC Scheme

Bench Top Measurements Oct. 2011, Wu Jinyuan, Fermilab A Novel Digitization Scheme with FPGA TDC for BLM 11

12 Cryogenic Ionization chamber 5k – 350K It is a helium-filled ionization chamber. It's current is proportional to the dose rate. ● The signal current is processed by a current to frequency converter to achieve a wide dynamic range and quick response dose rate excursions. ● All materials used are know to be radiation hard and suitable for operation at 5K. ● The electronics is self-contained and requires no computer to operate. A Novel Digitization Scheme with FPGA TDC for BLMOct. 2011, Wu Jinyuan, Fermilab

The chamber housing is held at negative potential and negative charge is collected on the center electrode. The HV is -95 V and is kept well below the minimum breakdown voltage of 156V in Helium. Cryogenic Loss Monitor operation The electronics uses a recycling integrator as a current to frequency converter with a wide dynamic range. The charge per pulse is 1.63pC or 238µR at 1 atm (room temp) of He. The recycling integrator consist of a charge integrating amplifier with a 0.50 pF capacitance followed by a discriminator which senses when the capacitor is fully charged. The FPGA generates a fixed-width (1.2µs) discharge pulse with an amplitude of 3.3V. It connects to the amplifier input via a 13 MΩ resistor, creating a 254 nA discharge current 13 A Novel Digitization Scheme with FPGA TDC for BLMOct. 2011, Wu Jinyuan, Fermilab

A Novel Digitization Scheme with FPGA TDC for BLM 14 Test Hardware NIM to LVDS Converter TDC Module

Pulses at 150 nA Oct. 2011, Wu Jinyuan, Fermilab A Novel Digitization Scheme with FPGA TDC for BLM 15

Pulses at 300 nA Oct. 2011, Wu Jinyuan, Fermilab A Novel Digitization Scheme with FPGA TDC for BLM 16

Input Current and Output Pulses Oct. 2011, Wu Jinyuan, Fermilab A Novel Digitization Scheme with FPGA TDC for BLM 17 Input Current 100 nA/div Output Pulses

Digitized Results Oct. 2011, Wu Jinyuan, Fermilab A Novel Digitization Scheme with FPGA TDC for BLM 18 I=Q/dt

Beam Test: Magnet Sweeping Caused Beam Loss (100 s) Oct. 2011, Wu Jinyuan, Fermilab A Novel Digitization Scheme with FPGA TDC for BLM 19 The test was performed in Fermilab A0 test facility. A magnet was swept twice to induce some beam losses. Beam losses are seen when the RF becomes on at 1 Hz.

Beam Test: Magnet Sweeping Caused Beam Loss (20 s) Oct. 2011, Wu Jinyuan, Fermilab A Novel Digitization Scheme with FPGA TDC for BLM 20 The first sweep is expanded as shown. Beam losses are seen when the RF becomes on at 1 Hz. No beam loss is seen when the magnetic field reaches “correct” values.

Beam Test: Magnet Sweeping Caused Beam Loss (0.2 s) Oct. 2011, Wu Jinyuan, Fermilab A Novel Digitization Scheme with FPGA TDC for BLM 21 Beam losses are seen when the RF becomes on at 1 Hz. The ionization chamber responds the beam loss relatively rapidly. The tail seems to be ion clean up process.

Reducing Analog Design Challenges with Digital Tricks Oct. 2011, Wu Jinyuan, Fermilab A Novel Digitization Scheme with FPGA TDC for BLM 22

Pulse Width with Small & Large Current Oct. 2011, Wu Jinyuan, Fermilab A Novel Digitization Scheme with FPGA TDC for BLM 23 When input current becomes large, the pulse width of the recycling integrator becomes large. The charge in each pulse also increases. It is easy to accommodate in digital processing. No need to face analog challenges in integrator circuit.

Digitization of both Leading Edge & Pulse Width Oct. 2011, Wu Jinyuan, Fermilab A Novel Digitization Scheme with FPGA TDC for BLM 24 Each hit contains 56 bits. Leading edge is digitized at 1 ns LSB with 40 bits (>1000 s) full range. Pulse width uses 16 bits to represent up to 65  s. Leading Edge Time (40 bits) Pulse Width Leading Edge Time (40 bits) Pulse Width CH0CH1CH2CH3CH4CH5CH6CH7

Self Zero-Suppression Oct. 2011, Wu Jinyuan, Fermilab A Novel Digitization Scheme with FPGA TDC for BLM 25

Self Zero-Suppression: No Beam Loss, No Data Oct. 2011, Wu Jinyuan, Fermilab A Novel Digitization Scheme with FPGA TDC for BLM 26 There are less than 600 data points recorded in this time frame.

Oct. 2011, Wu Jinyuan, Fermilab A Novel Digitization Scheme with FPGA TDC for BLM 27 Summary Using FPGA TDC to digitize recycling integrator improves system performance:  Faster response: Promoting ionization chambers from long time dosimeters to fast beam protection instruments.  Reduced analog design challenge.  Self Zero-suppression. The scheme is to be integrated into the real system.

The End Thanks

Pulse Width with Larger Input Current Oct. 2011, Wu Jinyuan, Fermilab A Novel Digitization Scheme with FPGA TDC for BLM 29

Suggestions Oct. 2011, Wu Jinyuan, Fermilab A Novel Digitization Scheme with FPGA TDC for BLM 30 Can the leading edge of the discriminator be seen at the NIM port? Will the output pulse width represent the charge pumped back?

Possible Circuit Oct. 2011, Wu Jinyuan, Fermilab A Novel Digitization Scheme with FPGA TDC for BLM 31 The width of the charge pulse signal is N*400 ns. In typical hysteresis setting with small input current, N is 3. When the input current is large, N could be 4 or larger. The OUT2NIM signal is an OR of the discriminator input and the charge pulse signals. Therefore, the leading edge of the NIM output represents the transition timing of the discriminator. The measured width of the NIM pulse will be rounded to 400 ns, and this is proportional to the charge.

Oct. 2011, Wu Jinyuan, Fermilab A Novel Digitization Scheme with FPGA TDC for BLM 32 TDC Using FPGA Logic Chain Delay This scheme uses current FPGA technology Low cost chip family can be used. (e.g. EP2C8T144C6 $31.68) Fine TDC precision can be implemented in slow devices (e.g., 20 ps in a 400 MHz chip). IN CLK

Oct. 2011, Wu Jinyuan, Fermilab A Novel Digitization Scheme with FPGA TDC for BLM 33 FPGA TDC A possible choice of the TDC can be a delay line based architecture called the Wave Union TDC implemented in FPGA. Shown here is an ASIC-like implementation in a 144-pin device. 18 Channels (16 regular channels + 2 timing reference channels). This FPGA cost $28, $1.75/channel. (AD9222: $5.06/channel) LSB ~ 60 ps. RMS resolution < 25 ps. Power consumption 1.3W, or 81 mW/channel. (AD9222: 90 mW/channel) In CLK Wave Union Launcher A

Oct. 2011, Wu Jinyuan, Fermilab A Novel Digitization Scheme with FPGA TDC for BLM 34 Measurement Result for Wave Union TDC A Histogram Raw TDC + LUT 53 MHz Separate Crystal -- Wave Union Histogram Plain TDC:  delta t RMS width: 40 ps.  25 ps single hit. Wave Union TDC A:  delta t RMS width: 25 ps.  17 ps single hit.

Oct. 2011, Wu Jinyuan, Fermilab A Novel Digitization Scheme with FPGA TDC for BLM Differential Inputs and Ramping Reference Voltage 35 TDC (Multi-Sampling) c0 c90 c180 c270 Encoder Recycling Integrator N dt

The Top Layer of the 1 ns TDC Oct. 2011, Wu Jinyuan, Fermilab A Novel Digitization Scheme with FPGA TDC for BLM 36