Characterization of Nanoscale Dielectrics or What characterizes dielectrics needed for the 22 nm node? O. Engstrom 1, M. Lemme 2, P.Hurley 3 and S.Hall.

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Presentation transcript:

Characterization of Nanoscale Dielectrics or What characterizes dielectrics needed for the 22 nm node? O. Engstrom 1, M. Lemme 2, P.Hurley 3 and S.Hall 4 1 Chalmers University of Technology 2 AMO GmbH 3 Tyndal Laboratories 4 Liverpool University

Questions at issue How long can HfO 2 be used? How to find the road to higher-k, higher offset dielectrics? Problems in connection with bulk and SOI

HfO 2

High-k Metal Gate AMO, Liverpool, Chalmers and Tyndall Ni Si HfO 2 Tyndall : e-beam evaporation Liverpool: MoCVD, ALD Chalmers: Reactive sputtering, ALD AMO: MBE & metallization

High-k Metal Gate SINANO Exchange: Tyndall  Chalmers Nov 2006 : Study of Bulk Defects in HfO 2 T ox (max/min) = 42.9Å/41.4Å  =0.15Å JV Dispersion: 65 sites 55umx55um (100)Si/SiO x (0.6nm)/HfO 2 (3.5nm)/Ni

(100)Si/SiO x /HfO 2 /TiN System Interface defects: Origin and Annealing p Sin Si P.K.Hurley, K. Cherkaoui, and A.W. Groenland “Electrically active interface defects in the (100)Si/SiOx/HfO2/TiN system: Origin, Instabilities and Passivation”, Invited paper: ECS, Cancun, Mexico, October 2006 SINANO Acknowledged HfO 2 by ALD

HfO 2 /TiN n channel MOSFETs Mobility degradation: Interface States D it = 4.0 x cm -2 I CP (1 MHz) -I CP (1 kHz) Interface states do not limit mobility (D IT <5.0 x cm -2 ) HfO 2 by ALD

HfO 2 /TiN n channel MOSFETs Mobility degradation Presented at EMRS Symposium L, 2006: SINANO acknowledged Temperature [K]  o [cm 2 /Vs]  sr cc  ph  o (fitting)  o (measured) Remote phonon scattering term limits mobility above temperature 50 K. Weber et al, Proc. ESSDERC, 2005, p. 379

Gavartin et al, JAP 97, (2005) Johansson et al, subm. JAP Oxide defects, ALD HfO 2

Mitrovic et al, manuscript submitted Hafnium silicate Spectroscopic ellipsometry Absorption constant [arb. units]

The road to higher k and higher band offset values

Scaling problem of the bulk MOSFET: Shorter channel length requires increased doping under the channel which requires higher capacitive coupling between gate and channel which in turn requires thinner gate insulator material

k=f( ) Clausius-Mosotti O. Engström, B. Raeissi, S. Hall, O. Buiu, M.C. Lemme, H.D.B. Gottlob, P.K. Hurley, K. Cherkaoui, Proc. ULIS, 2006, subm. To SSE

k=f( ) O. Engström, B. Raeissi, S. Hall, O. Buiu, M.C. Lemme, H.D.B. Gottlob, P.K. Hurley, K. Cherkaoui, Proc. ULIS, 2006, subm. To SSE

k=f( ) O. Engström, B. Raeissi, S. Hall, O. Buiu, M.C. Lemme, H.D.B. Gottlob, P.K. Hurley, K. Cherkaoui, Proc. ULIS, 2006, subm. To SSE

Offset value = f(heat of formation) O. Engström, B. Raeissi, S. Hall, O. Buiu, M.C. Lemme, H.D.B. Gottlob, P.K. Hurley, K. Cherkaoui, Proc. ULIS, 2006, subm. To SSE

The 22 nm node border Borders for the 22 nm LSTP node O. Engström, B. Raeissi, S. Hall, O. Buiu, M.C. Lemme, H.D.B. Gottlob, P.K. Hurley, K. Cherkaoui, Proc. ULIS, 2006, subm. To SSE

Gate insulators for SOI

H.D.B. Gottlob et al., IEEE EDL, Vol. 27, No. 10, October, 2006 ITRS targets for 2012 EOT given here for a quantum mechanical correction of CET by 0.3 nm Epitaxial Gd 2 O 3 with NiSi gate electrodes

Single gate Double gate From Risch, SSE 50, 527 (2006) SOI FD MOSFET LgLg x ”natural length”

E c [eV] x [nm] (a)  Source Drain x [nm] (b) Source Drain  Conduction band shape for an SOI FD DG MSFET

t Si [nm] L g / SiO 2 Gd 2 O 3 HfO 2 La 2 O 3 Silicon thickness for FD DG SOI MOSFETs in the 22 nm LSTP node

Sotomayor-Torres et al, Phys. Stat. Sol. 1, 2609 (2004) Donetti et al, JAP, 100, (2006) Uchida & Takagi, APL 82, 2916 (2003) Phonon and interface scattering in thin silicon layers Phonon modes Theory Mobility

Summary High-k for the 22 nm LSTP node Bulk: –So far only La 2 O 3, LaAlO 3 seem to pass SOI: –SiO 2 cannot be used neither for DG nor GAA –Probably HfO 2 can be used for GAA –For DG La 2 O 3 seems to be necessary, but Gd 2 O 3 may be an alternative Brask-lapp: Things may change!