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TEMPLATE DESIGN © 2008 www.PosterPresentations.com High-k Dielectric Process to Minimize Mobile Ionic Penetration David W. Parent, Eric Basham, Janet Davis.

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Presentation on theme: "TEMPLATE DESIGN © 2008 www.PosterPresentations.com High-k Dielectric Process to Minimize Mobile Ionic Penetration David W. Parent, Eric Basham, Janet Davis."— Presentation transcript:

1 TEMPLATE DESIGN © 2008 www.PosterPresentations.com High-k Dielectric Process to Minimize Mobile Ionic Penetration David W. Parent, Eric Basham, Janet Davis Department of Electrical Engineering, San Jose State university, San Jose, California 95192. Introduction The nMOS field effect transistor configured as a high gain amplifier can be used to amplify microvolt signals from neurons 1. To increase the gain of the amplifier, the use of a high-k dialectic material, such as hafnium oxide (HfO) is explored. Integration of the MOSFET with the neuron provides the ability to record neural signals. This can further understanding of how they transmit and process data efficiently. Research for interfacing neurons to transistors has been conducted in the past, however, open gate transistors using standard SiO 2 as the gate dielectric suffer from drift due to mobile species ionic penetration 2. Furthermore, SiO 2 degrades over time when introduced in a biological environment. Because HfO is non reactive and has good biocompatibility, it is a good candidate for use in biological applications 3. In addition, it is a high-k dielectric material which has the benefit of increasing the gain of the transistor. This structure is shown below. Methodology Results Summary Key References Acknowledgements A process for fabricating HfO films was developed and tested. A 333Å HfO film was successfully deposited and its C-V plots were extracted. The dielectric constant was lower than expected. This could be due to the formation of an interfacial layer. With the fabrication process verified, HfO and SiO 2 films can be fabricated and characterized. The high-k of hafnium will allow for fabrication of a high gain transistor that is more resistant to ionic penetration. These conditions make the transistor suitable for interfacing with a neuron to record neural activity. [1] D. Parent and E. Basham, "Hafnium transistor design for neural interfacing," in Engineering in Medicine and Biology Society, 2008. EMBS 2008. 30th Annual International Conference of the IEEE, 2008, pp. 3356- 3359. [2] Miremadi, B.K., S.R. Morrison, and K. Colbow, Stabilization of silicon-based devices in ion-containing media using thin Al2O3 platelets and MoS2 oriented thin films. Applied Physics A: Materials Science & Processing, 1995. 62(1): p. 39-42. [3] Matsuno, H., et al., Biocompatibility and osteogenesis of refractory metal implants, titanium, hafnium, niobium, tantalum and rhenium. Biomaterials, 2001. 22(11): p. 1253-1262. [4] Blanchin, M.G., et al., Structure and dielectric properties of HfO2 films prepared by a sol–gel route. Journal of Sol-Gel Science and Technology, 2008. 47(2): p. 165-172. The authors wish to thank Craig Stauffer for his assistance in machining the components for the evaporator. Thanks to Neil Peters for support in the Microelectronics Process Engineering Laboratory (MPEL). This work was supported by Defense Microelectronics Activity Cooperative Agreement # H94003-08-2-0806-SJSU. HfO films for MOS capacitor shave been previously fabricated but were damaged before characterization 4. This work seeks to fabricate HfO films for MOS capacitors using improved equipment for better film quality. In addition, film characterization via C-V, C-T, and TVS will be performed. Film Growth Synopsis TCAD software was used to model the physical behavior of the MOS capacitor. The target oxide thickness for both the hafnium and silicon films was 400Å. A 1-D TCAD simulation was used to extract the N A, V T, and Q ss. Source V T (V) SiO 2 HfO Hand Calculations2.970.53 TCAD2.760.69 To correct this, prior to evaporation, the boats were pretreated by placing a small amount of hafnium in the boat and bringing the temperature up to the melting point of hafnium for a short period. This resulted in a hafnium coating that had partially diffused into the tungsten and reacted to form a barrier to preventing addition hafnium from diffusing through during evaporation. To deposit films a separate evaporator was built with added components to increase the control over the growth of the film: Quartz Crystal Microbalance (QCM) to monitor the thickness Residual Gas Analyzer (RGA) to monitor gas composition Shutter control to control the amount of material being deposited. This provides additional control of the thickness of the film Cooling jacket to act as a heat sink and protect the gaskets in the system The film was then annealed at 800 °C. The resulting C-V plot is shown below and the dielectric constant was found to be 10.5. To verify the procedure for thermally evaporating HfO in the evaporator previously shown, a control sample was created. A HfO film was grown on top of a orientation p-type substrate and a film of 333Å was achieved. The EDAX spectrum was collected as shown below. The films were grown using thermal evaporation. Tungsten boats were used for evaporating the hafnium. However, the hafnium diffused through the tungsten and caused breakage. The total capacitance is made up of the series capacitance of the HfO and the SiO 2. Since the ε siO2 value of the SiO 2 interfacial layer is small, it can reduce the overall capacitance which in turn reduces the extracted value for the dielectric constant. If an interfacial layer is assumed, the dielectric constant can be calculated using the equations below. Assuming an interfacial layer of 10Å and an ε ox of 3.9, the dielectric constant of the film was found to be 18. Capacitance versus Voltage (C-V): A plot of the capacitance versus voltage will be used to extract the V FB, V T, t ox, and Q ss parameters. Methodology To characterize the SiO 2 and HfO MOS capacitors, the following test will be performed: Triangular Voltage Sweep (TVS): The TVS test is used to determine the amount of sodium contamination present in the MOS capacitor. Capacitance versus Time (C-T): This test will monitor the MOS capacitor’s ability to maintain its capacitance over time in the presence of sodium. The ε ox value from the TCAD simulation was based upon the previous work. The fact that the ε ox of this experiment is lower can be attributed to an interfacial layer 4. The film was then characterized using the C-T test to see how well the capacitance is maintain over time when exposed to a 0.5M saline solution. The capacitance remained fairly constant over time for different bias voltages. In addition, there appeared to be no significant shift in the C-V curve before and after exposure to the saline solution. The conductance of the film before and after the C-T tests was also plotted and it was noted that there was no significant shift.


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