Prediction W. Buchmueller (DESY) arXiv:hep-ph/9912317 (1999)

Slides:



Advertisements
Similar presentations
Kondo GNANVO Florida Institute of Technology, Melbourne FL.
Advertisements

Application of the DRS Chip for Fast Waveform Digitizing Stefan Ritt Paul Scherrer Institute, Switzerland.
A scalable DAQ system using the DRS4 sampling chip H.Friederich 1, G.Davatz 1, U.Hartmann 2, A.Howard 1, H.Meyer 1, D.Murer 1, S.Ritt 2, N.Schlumpf 2 1.
Test of LLRF at SPARC Marco Bellaveglia INFN – LNF Reporting for:
28 August 2002Paul Dauncey1 Readout electronics for the CALICE ECAL and tile HCAL Paul Dauncey Imperial College, University of London, UK For the CALICE-UK.
DSP online algorithms for the ATLAS TileCal Read Out Drivers Cristobal Cuenca Almenar IFIC (University of Valencia-CSIC)
Design and Performance of the 6 GS/s Waveform Digitizing Chip DRS4 Stefan Ritt Paul Scherrer Institute, Switzerland at 40 mW per channel.
Large Area, High Speed Photo-detectors Readout Jean-Francois Genat + On behalf and with the help of Herve Grabas +, Samuel Meehan +, Eric Oberla +, Fukun.
Low Cost TDC Using FPGA Logic Cell Delay Jinyuan Wu, Z. Shi For CKM Collaboration Jan
July 16/17, 2002 MUEGAMMA review PSI1 Slow Control.
1 DAQ Update. 2 DAQ Status DAQ was running successfully and stably in ’07 beam time Trigger bus scheme has proven to be very flexible – Added additional.
Fast Waveform Digitizing in Radiation Detection using Switched Capacitor Arrays Stefan Ritt Paul Scherrer Institute, Switzerland.
Shuei MEG review meeting, 2 July MEG Software Status MEG Software Group Framework Large Prototype software updates Database ROME Monte Carlo.
1 S. E. Tzamarias Hellenic Open University N eutrino E xtended S ubmarine T elescope with O ceanographic R esearch Readout Electronics DAQ & Calibration.
06/03/06Calice TB preparation1 HCAL test beam monitoring - online plots & fast analysis - - what do we want to monitor - how do we want to store & communicate.
DLS Digital Controller Tony Dobbing Head of Power Supplies Group.
The Trigger Prototype Board Status Marco Grassi INFN - Pisa On behalf of trigger group D. Nicolò F. Morsani S. Galeotti M. Grassi.
UCN-nEDM DAQ DAQ and Slow Control L.Lee 1 July 3, 2013.
14/02/2007 Paolo Walter Cattaneo 1 1.Trigger analysis 2.Muon rate 3.Q distribution 4.Baseline 5.Pulse shape 6.Z measurement 7.Att measurement OUTLINE.
DC12 Commissioning Status GOALS: establish operating conditions, determine initial calibration parameters and measure operating characteristics for the.
14 February 2007Fabrizio Cei1 INFN and University of Pisa PSI Review Meeting PSI, 14 February 2007 Status of MEG Software.
DAQ+trigger operation during 2008 run D. Nicolò University of Pisa & INFN, Pisa.
M&O status and program for ATLAS LAr calorimeter R Stroynowski (on vacations)
March 6, INST02, Novosibirsk1 Electronics for the  e  experiment at PSI Short introduction Trigger electronics DAQ electronics Slow Control For the.
GAYA Analyzer SDD Presentation. GAYA Analyzer Introduction OMS40G256 is a hardware device used for detection of radioactive radiation for medical imaging.
The DRS2 Chip: A 4.5 GHz Waveform Digitizing Chip for the MEG Experiment Stefan Ritt Paul Scherrer Institute, Switzerland.
Dec.11, 2008 ECL parallel session, Super B1 Results of the run with the new electronics A.Kuzmin, Yu.Usov, V.Shebalin, B.Shwartz 1.New electronics configuration.
1 DAQ Update MEG Review Meeting, Feb. 17 th 2010.
12 October 2001, M. LefebvreHEC-Athena Tutorial: HEC beam test primer1 HEC Beam Test Primer Production modules of the HEC have been tested in particle.
PSD upgrade: concept and plans - Why the PSD upgrade is necessary? - Concept and status of the PSD temperature control - Concept of the PSD analog part.
Florida Institute of Technology, Melbourne, FL
Front-End Electronics for G-APDs Stefan Ritt Paul Scherrer Institute, Switzerland.
TYPE1 BOARD Type1 boards are compliant with 6U VME standard. Each board receives 16 analog signals from experimental devices. These signals are digitized.
MEG trigger system This short presentation describes the present status of the trigger algorithms of the MEG experiment implemented on the Xilinx FPGA.
PSI - 11 Feb Status of the electronic systems of the MEG Experiment.
Kevin Nash MaPSA-Light test system 1. The System 2.
TDAQ Experience in the BNL Liquid Argon Calorimeter Test Facility Denis Oliveira Damazio (BNL), George Redlinger (BNL).
DOM MB Test Results at LBNL Main Board Readiness Status Review LBNL, July 2003 Azriel Goldschmidt.
1 Electronics Status Trigger and DAQ run successfully in RUN2006 for the first time Trigger communication to DRS boards via trigger bus Trigger firmware.
The MEG Offline Project General Architecture Offline Organization Responsibilities Milestones PSI 2/7/2004Corrado Gatto INFN.
Status of the PSD upgrade - Status of the PSD cooling and temperature stabilization system - MAPD gain monitoring system - PSD readout upgrade F.Guber,
PSD upgrade: concept and plans - Why the PSD upgrade is necessary? - Concept of the PSD temperature stabilization and control - Upgrade of HV control system.
Overview of PHENIX Muon Tracker Data Analysis PHENIX Muon Tracker Muon Tracker Software Muon Tracker Database Muon Event Display Performance Muon Reconstruction.
Pisa - Apr. 28th, The Trigger System Marco Grassi INFN - Pisa.
Level-1 Trigger Commissioning Status A.Somov Jefferson Lab Collaboration Meeting, May 10, 2010.
THE WaveDAQ SYSTEM FOR THE MEG II UPGRADE … read out by MIDAS Stefan Ritt, Paul Scherrer Institute, Switzerland 15 July 2015MIDAS Workshop, TRIUMF Paul.
IEEE Real Time 091 Data Acquisition System for Multi-channel Gas Detector Hongyu ZHANG, Kejun ZHU, Haitao ZHU Institute of High Energy Physics,
PHOTOTUBE SCANNING SETUP AT THE UNIVERSITY OF MARYLAND Doug Roberts U of Maryland, College Park.
Analog Trigger for CTA MST CTA MST Trigger & Integration Meeting Berlin, 7 November 2011 Luis A. Tejedor on behalf of GAE-UCM, IFAE & CIEMAT groups 1.
Software Design of Electronics Tests and Data Acquisition for a New Gas Detector ZHAO Dongxu 1, 2 ZHANG Hongyu 2 YUE Xiaobo 1 ZHAO Yubin 2 CHEN Yuanbo.
DAQ and Trigger for HPS run Sergey Boyarinov JLAB July 11, Requirements and available test results 2. DAQ status 3. Trigger system status and upgrades.
MADEIRA Valencia report V. Stankova, C. Lacasta, V. Linhart Ljubljana meeting February 2009.
Slow Control and Run Initialization Byte-wise Environment
Slow Control and Run Initialization Byte-wise Environment
Baby-Mind SiPM Front End Electronics
Marcin Chrząszcz Cracow University of Technology Itamar Levy
ETD meeting Electronic design for the barrel : Front end chip and TDC
Ongoing R&D in Orsay/Saclay on ps time measurement: a USB-powered 2-channel 3.2GS/s 12-bit digitizer D.Breton (LAL Orsay), E.Delagnes (CEA/IRFU) Séminaire.
Hellenic Open University
Possible Upgrades ToF readout Trigger Forward tracking
Front-end electronic system for large area photomultipliers readout
Status of n-XYTER read-out chain at GSI
Technische Universität München
Commodity Flash ADC-FPGA Based Electronics for an
CLAS12 Timing Calibration
BESIII EMC electronics
Stefan Ritt Paul Scherrer Institute, Switzerland
The Trigger System Marco Grassi INFN - Pisa
The CMS Tracking Readout and Front End Driver Testing
Trigger operation during 2007 run
Presentation transcript:

Prediction W. Buchmueller (DESY) arXiv:hep-ph/ (1999)

Computing DC track reconstruction Slow control system DRS sampling chip Software framework DC track reconstruction Slow control system DRS sampling chip Software framework

Pattern Finding & Track Fitting Basic Track Fitting done in Pisa MC PSI will concentrate on building the DC and on noise minimization, but not on PF & TF Interface:  /r/z from waveform analysis done at PSI Basic Track Fitting done in Pisa MC PSI will concentrate on building the DC and on noise minimization, but not on PF & TF Interface:  /r/z from waveform analysis done at PSI

Labview control of Large Prototype MSCB Bus works stable Hardware in bulk production Used by 3 other experiments at PSI MSCB Bus works stable Hardware in bulk production Used by 3 other experiments at PSI

Domino Ring Sampler (DRS) Free running domino wave, stopped with trigger Sampling speed 2 GHz (500ps/bin), trigger gate sampling gives 50ps timing resolution 1024 bins  150ns waveform + 350ns delay 40 MHz readout Free running domino wave, stopped with trigger Sampling speed 2 GHz (500ps/bin), trigger gate sampling gives 50ps timing resolution 1024 bins  150ns waveform + 350ns delay 40 MHz readout Enable In

DRS Tests Sampling Speed 0.7 – 2.5 GHz Power Supply 35mW 6mW Timing jitter: 100ps Sampling Speed 0.7 – 2.5 GHz Power Supply 35mW 6mW Timing jitter: 100ps Readout stable at 40 MHz TC: 0.2% / deg. C Readout stable at 40 MHz TC: 0.2% / deg. C

Test Pulse Readout 12ns Input pulses Limited by readout cirquitry!

Domino Wave Stabilization DLL Phase and Frequency Stabilization External Common Reference Clock V speed 8 inputs shift register Trigger Signal Sampling trigger gate domino wave FAD C MUX

Schedule July 2002: Jan 2003: Test Milestone AssemblyDesignManufactoring 2 nd Prototype 1 st Prototype Boards 2 nd Prototype Tests1 st Prototype Boards

Software Framework

HOWTO Questions (A. Blondel) Process MC events through analysis chain Handle calibration constants, bookkeeping and monitoring Visualize single events “Harmonize” software, have same framework in Japan, Italy and PSI Description of current software (beam tests) Organization to develop software Data processing capabilities Process MC events through analysis chain Handle calibration constants, bookkeeping and monitoring Visualize single events “Harmonize” software, have same framework in Japan, Italy and PSI Description of current software (beam tests) Organization to develop software Data processing capabilities

Analyzing MC Data Shared memory Frontend Logger Analyzer “Staged” MIDAS analyzer MIDAS structure Pedestal Subtraction Online data Calibration Energy Summing Physics Cuts storage Histogram Display PAW/Root Single Event Display Histograms MC particles MC PMT Shared memory PAW Data FileAnalyzer PAW N-tuple File online offline MC Waveform Data File

Online Database ODB Calibration constants, SW+HW Configuration Frontend Logger Analyzer Frontend Online Offline ODB Calibration constants, SW+HW Configuration Analyzer Run1Run2Run3Run4CalibACalibBCalibC Data file

Bookkeeping with ELOG

Monitoring MIDAS History Trendlines over time Slow control (temperatures, pressures, etc.) Scaler ratios Efficiencies “Physics” rates MIDAS History Trendlines over time Slow control (temperatures, pressures, etc.) Scaler ratios Efficiencies “Physics” rates

Alarm System Integrated into MIDAS DAQ Slow control variables and analyzer variables Connected to pager system Integrated into MIDAS DAQ Slow control variables and analyzer variables Connected to pager system

 Single Event Display  e

Software organization Analyzer contains “common” and “private” modules Three “software managers” (Japan, Italy, PSI) maintain software locally and decide about common modules Algorithms are developed inside MC and converted to analyzer modules Revision management with CVS MC upgrade: Pisa? Single event display: small task for one person Analyzer contains “common” and “private” modules Three “software managers” (Japan, Italy, PSI) maintain software locally and decide about common modules Algorithms are developed inside MC and converted to analyzer modules Revision management with CVS MC upgrade: Pisa? Single event display: small task for one person

Processing capabilities Assume: 100 Hz trigger, 50% occupancy (LXe) and 10% occupancy (DC) Data: 1.2MB/event or 120MB/sec Online Linux cluster: each node <10MB/sec 3 rd level trigger: waveforms only for  e  candidates stored, else ADC/TDC analysis (  10kB/event) Waveform compression: 10x 90Hz ADC/TDC data, 10Hz waveform data 10 x 1.2MB x x 0.01MB = 2.1 MB Assume: 100 Hz trigger, 50% occupancy (LXe) and 10% occupancy (DC) Data: 1.2MB/event or 120MB/sec Online Linux cluster: each node <10MB/sec 3 rd level trigger: waveforms only for  e  candidates stored, else ADC/TDC analysis (  10kB/event) Waveform compression: 10x 90Hz ADC/TDC data, 10Hz waveform data 10 x 1.2MB x x 0.01MB = 2.1 MB

Software Framework Summary Existing –Online DAQ system –History system –Alarm system –Electronic logbook –Analyzer framework –PAW histogram display –Used in Japan, PSI, Pisa Elaborate MC Existing –Online DAQ system –History system –Alarm system –Electronic logbook –Analyzer framework –PAW histogram display –Used in Japan, PSI, Pisa Elaborate MC Req uired –Single Event Display (1-2 PM) –MC interface to DAQ (1 PW) –MC “upgrade” (noise, inefficiencies, pileup) –Track reconstruction –Analyzer modules Req uired –Single Event Display (1-2 PM) –MC interface to DAQ (1 PW) –MC “upgrade” (noise, inefficiencies, pileup) –Track reconstruction –Analyzer modules