Electronic System Design GroupInstrumentation DepartmentR. Halsall, S. Taghavirad et alRutherford Appleton Laboratory5 March 2003 Delay FPGA I/O Clock40 Reset ADC_Data_stream_0 ADC_Data_stream_3 Delay FPGA delay_ser_out delay_ser_in Configuration JTAG TEMP SENSE - NFBank Drive Voltages Core Voltage, gnd Bank DCI Resistors 10 busy Clock XC2V80FG I/O XC2V40CS I/O Design I/O Total = 73+ ADC_Data_stream_0 ADC_Data_stream_3 5 5 Configuration Bank Ref Voltages 2 Non I/O pins Multi function

Electronic System Design GroupInstrumentation DepartmentR. Halsall, S. Taghavirad et alRutherford Appleton Laboratory5 March 2003 Delay FPGA Function REG 10 REG DCM 0 REG SHIFT REG 10 REG DCM 3 IOB REG SHIFT REG 5 Slices 1 4 DPM BLOCK RAM 0 REG IOB DPM BLOCK RAM 3 IOB Counter IOB CONTROL REG CLOCK - 40 MHz RESET Serial In Serial Out busy DATA OUT 0 DATA OUT 3 DCI CLOCK OUT 0 CLOCK OUT 3 2.5/3.3V I/O? 1.5/1.8/2.5/3.3V I/O? Control Clock Counter 10 Slices XC2V40-CS phases

Electronic System Design GroupInstrumentation DepartmentR. Halsall, S. Taghavirad et alRutherford Appleton Laboratory5 March 2003 CMS Tracker FED Firmware Front End FPGA I/O Frame_Sync_out Frame_Sync_In Readout_Sync_out Readout_Sync_In Data_stream Clock40 LVDS ADC_Data_stream_0 ADC_Data_stream_11 Full Flags Front End FPGA delay_ser_out delay_ser_in JTAG Temp Sense Bank Voltages Core Voltage busy Clock adc enables18 3 Opto Rx6 2 x Temp Sense DAC Serial 4 8 Power downVBatt Configuration Bank DCI Resistors Config_out (Config_Monitor_Out) Config_In (Config_Monitor_In) Monitor_in (DCM Reset) Monitor_out (Synch Reset) FE - BE I/O 12 signals

Electronic System Design GroupInstrumentation DepartmentR. Halsall, S. Taghavirad et alRutherford Appleton Laboratory5 March 2003 CALICE Firmware Front End FPGA I/O Frame_Sync_out Frame_Sync_In (Trigger) Readout_Sync_out Readout_Sync_In Data_stream Clock40 ADC_Data_stream_0 ADC_Data_stream_11 Full Flags Front End FPGA JTAG Temp Sense Bank Voltages Core Voltage Clock 403 adc control x 3 Power downVBatt dac controlx Temp monitor LVDS I/O Configuration Bank DCI Resistors Config_out (Config_Monitor_Out) Config_In (Config_Monitor_In) Monitor_in (DCM Reset) Monitor_out (Synch Reset) FE - BE I/O 12 signals

Electronic System Design GroupInstrumentation DepartmentR. Halsall, S. Taghavirad et alRutherford Appleton Laboratory5 March 2003 CMS Tracker FED FPGA Firmware Back End FPGA I/O Frame_Sync_out0 Frame_Sync_in 0 Readout_Sync_out0 Readout_Sync_In0 Sync Reset DCM Reset out 0 Data_stream0 Clock40 DCM Reset FE0 FE7 SLINK64 TTS VME SLINK ADDR/CNTRL DATA IN DATA OUT QDR SSRAM TTCrx BSCAN SLINK Temp Sense diode Bank Voltages Core Voltage Bank DCI Resistors 12 x2 QDR Common Address Load_Monitor_In 0 Load_monitor_out 0 Full flags3 Temp Flag LM Clock x 2 LVDS ef, pf & ff ‘I2C’ Single ended DCI J0 J2 4 pairs pairs Serial VME 32 TTC/S control interrupt Spare & Test Trig J03 pairs 18 Control Frame_Sync_out 7 Frame_Sync_in 7 Readout_Sync_out 7 Readout_Sync_In 7 Sync Reset DCM Reset out 7 Data_stream 7 Load_monitor_In 7 Load_monitor_out spare

Electronic System Design GroupInstrumentation DepartmentR. Halsall, S. Taghavirad et alRutherford Appleton Laboratory5 March 2003 CMS Tracker FED FPGA Firmware Back End FPGA Overview Frame_Syncs Readout_Syncs Synch/DCM Reset TTC Rx TTS 9 CONTROL Data_stream 0 Data_stream 7 64 Data In Address Data Out 8 SLINK 64 Pipelined Address Generator Data 80 MHz 4 4 Clock40 VME Clock Management x1 x2 QDR SSRAM x2/x4 burst 160 MHz 640 MHz 8x Lengths, Pointers FF/PF Flags 2 32 Control Serial I/O Load_monitor x DataControl Fill/run/freeze FF, PF, busy Clock40 FE 6 spare Pipelined Data Mux 64 2 x x 18 x8 VME Front End TTX SLINK 8 LVDS Clock40 TTC Channel Link 160 MHz Clock40 J0 QDR interrupt VME SLINK

Electronic System Design GroupInstrumentation DepartmentR. Halsall, S. Taghavirad et alRutherford Appleton Laboratory5 March 2003 CMS Tracker FED FPGA Firmware Back End FPGA Control Block Frame Sync Interface Readout Sync Interface Flow Control Interface VME Serial I/O P2p Serial Control FS in 0..7 RS in 0..7 FE FPGA FF/PF 0..1 TTS 0..X FS out 0..7 RS out 0..7 Resets Header Generation Header Data tap 0..X SLINK-VME SLINK Data TTC Interface TTC 0..9 DIagnostics SLINK Serial Interface Load_Monitor 0..7 SLINK QDR ADDR/CTRL SLINK QDR Data QDR Addr

Electronic System Design GroupInstrumentation DepartmentR. Halsall, S. Taghavirad et alRutherford Appleton Laboratory5 March 2003 CMS Tracker FED FPGA Firmware Back End FPGA Control Block Serial Detect Compare FS in 0..7 FIFO 512x80 CTRL HEADER fs_strobe, status= good, some header errors, arrival time error, fatal error fs_fifo_empty, fs_fifo_full, fifo_data=median header+status DPM 1K VME SERIAL 8x Serial Data, markers & control data circular buffer reset, freeze CSR

Electronic System Design GroupInstrumentation DepartmentR. Halsall, S. Taghavirad et alRutherford Appleton Laboratory5 March 2003 Readout Sync Serial Detect RS in 0..7 FIFO 8K CTRL BUS HEADER rs_strobe, status= good, arrival time error, fatal error copy_fifo_empty, copy_fifo_full, fifo_data= sub_lengths DPM 1K VME Serial 8x Serial Data, markers & control data circular buffer reset, freeze,readout_next RS out 0..7 FIFO 8K fifo_data= 8x sub_lengths FIFO 8K fifo_data= 8x pointer_offsets FIFO 1K Address Gen Total_length_fifo_empty, total_length_fifo_full, fifo_data= total length

Electronic System Design GroupInstrumentation DepartmentR. Halsall, S. Taghavirad et alRutherford Appleton Laboratory5 March 2003 Flow Control core FE FPGA PF TTS BUSY Addr GEN FF FE FPGA FF Internal FIFO FF Internal FIFO PF Internal Freeze Latch Fill Flow Control Internal FIFO EF SLINK CTRL Busy Empty Flow Control Addr GEN EF Addr GEN Controls RS Controls Internal Freeze Addr Gen FIFO PF Addr Gen FIFO FF Simplest flow control; Halt on any buffer full Busy on any buffer partially full Simplest flow control; Halt on any buffer full Busy on any buffer partially full Addr GEN Busy VME soft reset Circular Buffers Serial Fill event Readout event Diagnostic Event Logger Control Registers Time stamped TTS ERROR

Electronic System Design GroupInstrumentation DepartmentR. Halsall, S. Taghavirad et alRutherford Appleton Laboratory5 March 2003 TTC Interface TTC Interface TTC 0..9 FIFO 1K FIFO 1K DPM 1K Header VME Serial CTRL BUS ttc_strobe reset, freeze Bx,Ex Em Hdr

Electronic System Design GroupInstrumentation DepartmentR. Halsall, S. Taghavirad et alRutherford Appleton Laboratory5 March 2003 VME FPGA VME INT BE FPGA ParallelBE FPGA Serial System ACE Address/control data Temp Sense 32 Serial I/Ocontrol wait data Int Clock Management BE FPGA CSR I2C XTAL J0 SYS ACE Clock 40 burst Temp SensorEEPROM 6 spare

Electronic System Design GroupInstrumentation DepartmentR. Halsall, S. Taghavirad et alRutherford Appleton Laboratory5 March 2003 VME-BE-Parallel VME-SLINK Interface ‘VME’ BUS SLINK Data from BE FPGA QDR Event Data moved in blocks into DPM Burst transfer over VME Wait on software handshake before continuing Double buffered DPM 1K FIFO 1K 32 wait burst lengths data

Electronic System Design GroupInstrumentation DepartmentR. Halsall, S. Taghavirad et alRutherford Appleton Laboratory5 March 2003 VME-BE-Serial Serial I/O Engine Serial in 0..7 DPM 1K ‘VME’ BUS Output Serial out 0..7 DPM 1K Input

Electronic System Design GroupInstrumentation DepartmentR. Halsall, S. Taghavirad et alRutherford Appleton Laboratory5 March 2003 HeaderData ADC Output Frame Sync Status Message CMS Tracker FED System Timing Handshake Message Frame Sync In Readout Sync In Processed Message Readout Message #2234 #2233 #2220#2221 Data Burst #2220#2221 Data Data Burst #2219 Frame Sync Out Median header+ Accept/abort Length Readout Sync Out Next/delete NB Frame Sync In - Abort/Accept not used, auto accepts. Readout Sync In - delete not used.

Electronic System Design GroupInstrumentation DepartmentR. Halsall, S. Taghavirad et alRutherford Appleton Laboratory5 March 2003 CMS Tracker FED Back End FPGA Read Ptr Write Ptr 0 Write Ptr 1 Write Ptr 2 Write Ptr 7 Read Ptr Write Ptr 0 Write Ptr 1 Write Ptr 2 Write Ptr 7 Event N-1 Event N+1 Event N-1 Read Ptr Write Ptr 0 Write Ptr 1 Write Ptr 2 Write Ptr 7 Event N-1 Event N+1 #00000 #FFFFF Event N FE 0 FE 1 FE 7 T0T1T2

Electronic System Design GroupInstrumentation DepartmentR. Halsall, S. Taghavirad et alRutherford Appleton Laboratory5 March 2003 CMS Tracker FED - Back End FPGA Floorplan FE_FPGA_Inputs SLINK QDR XC2V1500FG I/O XC2V1000FG I/O XC2V2000FG I/O XC2V3000FG I/O Same frame 456 & 676 ? Clocks DiePackage VME